1. 10 Dec, 2019 11 commits
    • Thomas Zimmermann's avatar
      drm/ast: Move modesetting code to CRTC's atomic_flush() · 71d873cc
      Thomas Zimmermann authored
      When enabling the CRTC after waking up from a power-saving mode, the
      primary plane's framebuffer might be NULL, which leads to a stack trace
      as shown below.
      
        [  632.624608] BUG: kernel NULL pointer dereference, address: 0000000000000048
        [  632.624631] #PF: supervisor read access in kernel mode
        [  632.624639] #PF: error_code(0x0000) - not-present page
        [  632.624647] PGD 0 P4D 0
        [  632.624654] Oops: 0000 [#1] SMP PTI
        [  632.624662] CPU: 0 PID: 2082 Comm: gnome-shell Tainted: G            E     5.4.0-rc7-1-default+ #114
        [  632.624673] Hardware name: Sun Microsystems SUN FIRE X2270 M2/SUN FIRE X2270 M2, BIOS 2.05    07/01/2010
        [  632.624689] RIP: 0010:ast_crtc_helper_atomic_enable+0x7d/0x680 [ast]
        [  632.624698] Code: 48 8b 80 e0 02 00 00 4c 8b 60 10 31 c0 f3 48 ab 48 8b 83 78 04 00 00 4c 89 ef 48 8d 70 18 e8 9a e9 55 ce 48 8b 83 78 04 00 00 <49> 8b 7c 24 48 4c 89 ea 4c 8d 44 24 28 48 8d 4c 24 20 48 8d 70 18
        [  632.624718] RSP: 0018:ffffbe9ec123fa40 EFLAGS: 00010246
        [  632.624726] RAX: ffff95a13cfd3400 RBX: ffff95a13cf32000 RCX: 0000000000000000
        [  632.624735] RDX: 0000000000000000 RSI: ffff95a13cfd34e8 RDI: ffffbe9ec123fb40
        [  632.624744] RBP: ffffbe9ec123fb80 R08: 0000000000000000 R09: 0000000000000003
        [  632.624753] R10: 0000000000000000 R11: 0000000000000000 R12: 0000000000000000
        [  632.624762] R13: ffffbe9ec123fa70 R14: ffff95a13beb7000 R15: ffff95a13cf32800
        [  632.624772] FS:  00007f6d2763e140(0000) GS:ffff95a134000000(0000) knlGS:0000000000000000
        [  632.624782] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
        [  632.624790] CR2: 0000000000000048 CR3: 00000001192f8004 CR4: 00000000000206f0
        [  632.624800] Call Trace:
        [  632.624811]  ? __lock_acquire+0x409/0x7c0
        [  632.624830]  drm_atomic_helper_commit_modeset_enables+0x1af/0x200
        [  632.624840]  drm_atomic_helper_commit_tail+0x32/0x70
        [  632.624849]  commit_tail+0xc7/0x110
        [  632.624857]  drm_atomic_helper_commit+0x121/0x130
        [  632.624867]  drm_atomic_connector_commit_dpms+0xd7/0x100
        [  632.624878]  set_property_atomic+0xaf/0x110
        [  632.624890]  drm_mode_obj_set_property_ioctl+0xbb/0x190
        [  632.624899]  ? drm_mode_obj_find_prop_id+0x40/0x40
        [  632.624909]  drm_ioctl_kernel+0x86/0xd0
        [  632.624918]  drm_ioctl+0x1e4/0x36b
        [  632.624925]  ? drm_mode_obj_find_prop_id+0x40/0x40
        [  632.624939]  do_vfs_ioctl+0x4bd/0x6e0
        [  632.624949]  ksys_ioctl+0x5e/0x90
        [  632.624957]  __x64_sys_ioctl+0x16/0x20
        [  632.624966]  do_syscall_64+0x5a/0x220
        [  632.624976]  entry_SYSCALL_64_after_hwframe+0x49/0xbe
        [  632.624984] RIP: 0033:0x7f6d2b0de387
        [  632.624991] Code: 00 00 90 48 8b 05 f9 9a 0c 00 64 c7 00 26 00 00 00 48 c7 c0 ff ff ff ff c3 66 2e 0f 1f 84 00 00 00 00 00 b8 10 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d c9 9a 0c 00 f7 d8 64 89 01 48
        [  632.625011] RSP: 002b:00007fffb49def38 EFLAGS: 00000246 ORIG_RAX: 0000000000000010
        [  632.625021] RAX: ffffffffffffffda RBX: 00007fffb49def70 RCX: 00007f6d2b0de387
        [  632.625030] RDX: 00007fffb49def70 RSI: 00000000c01864ba RDI: 0000000000000009
        [  632.625040] RBP: 00000000c01864ba R08: 0000000000000000 R09: 00000000c0c0c0c0
        [  632.625049] R10: 0000000000000030 R11: 0000000000000246 R12: 000055bc367eb920
        [  632.625058] R13: 0000000000000009 R14: 0000000000000002 R15: 0000000000000000
        [  632.625071] Modules linked in: ebtable_filter(E) ebtables(E) ip6table_filter(E) ip6_tables(E) iptable_filter(E) ip_tables(E) x_tables(E) af_packet(E) scsi_transport_iscsi(E) dmi_sysfs(E) msr(E) xfs(E) intel_powerclamp(E) coretemp(E) k)
        [  632.625185] CR2: 0000000000000048
      
      The STR is
      
      	* start gdm and wait for it to switch off the display
      	* wake up the display by pressing a key
      
      CRTC modesetting depends on the new state of the CRTC and the primary
      plane's framebuffer. The bugfix moves the modesetting code into the
      CRTC's atomic_flush() function, where it is protected from the plane's
      framebuffer being NULL.
      
      The CRTC's atomic-enable function, which is the modesetting's original
      location, still contains DPMS state handling. It's exactly the inverse
      of the atomic-disable function.
      
      v3:
      	* protect modesetting from from fb == NULL
      v2:
      	* do an atomic check for plane
      	* reject invisible primary planes
      Signed-off-by: default avatarThomas Zimmermann <tzimmermann@suse.de>
      Acked-by: default avatarGerd Hoffmann <kraxel@redhat.com>
      Fixes: b48e1b6f ("drm/ast: Add CRTC helpers for atomic modesetting")
      Cc: Gerd Hoffmann <kraxel@redhat.com>
      Cc: Dave Airlie <airlied@redhat.com>
      Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
      Cc: "Y.C. Chen" <yc_chen@aspeedtech.com>
      Cc: Sam Ravnborg <sam@ravnborg.org>
      Link: https://patchwork.freedesktop.org/patch/msgid/20191202111557.15176-2-tzimmermann@suse.de
      71d873cc
    • Neil Armstrong's avatar
      drm/meson: crtc: add OSD1 plane AFBC commit · c96bcb63
      Neil Armstrong authored
      Finally, setup the VIU registers and start the AFBC decoder to support
      displaying AFBC encoded buffers on Amlogic GXM and G12A SoCs.
      
      The RDMA is used here to reset and program the AFBC decoder unit
      on each vsync without involving the interrupt handler that can
      be masked for a long period of time, producing display glitches.
      
      The vsync irq must still be left enabled otherwise the RDMA modules isn't
      trigerred when the interrupt line is masked.
      Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
      Reviewed-by: default avatarKevin Hilman <khilman@baylibre.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20191021091509.3864-10-narmstrong@baylibre.com
      c96bcb63
    • Neil Armstrong's avatar
      drm/meson: hold 32 lines after vsync to give time for AFBC start · 24e0d405
      Neil Armstrong authored
      When using an AFBC encoded frame, the AFBC Decoder must be reset,
      configured and enabled at each vsync IRQ.
      
      To leave time for that, use the maximum lines hold time to give time
      for AFBC setup and avoid visual glitches.
      Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
      Reviewed-by: default avatarKevin Hilman <khilman@baylibre.com>
      [narmstrong: fix typo in commit log]
      Link: https://patchwork.freedesktop.org/patch/msgid/20191021091509.3864-9-narmstrong@baylibre.com
      24e0d405
    • Neil Armstrong's avatar
      drm/meson: viu: add AFBC modules routing functions · 1b85270f
      Neil Armstrong authored
      The Amlogic G12A AFBC Decoder pixel input need to be routed diferently
      than the Amlogic GXM AFBC decoder, this adds support for routing the
      VIU OSD1 pixel source to the AFBC "Mali Unpack" module.
      
      This "Mali Unpack" module is also configured with a static RGBA mapping
      for now until we support more pixel formats.
      Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
      Reviewed-by: default avatarKevin Hilman <khilman@baylibre.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20191021091509.3864-8-narmstrong@baylibre.com
      1b85270f
    • Neil Armstrong's avatar
      drm/meson: plane: add support for AFBC mode for OSD1 plane · 68e2f64e
      Neil Armstrong authored
      This adds all the OSD configuration plumbing to support the AFBC decoders
      path to display of the OSD1 plane.
      
      The Amlogic GXM and G12A AFBC decoders are integrated very differently.
      
      The Amlogic GXM has a direct output path to the OSD1 VIU pixel input,
      because the GXM AFBC decoder seem to be a custom IP developed by Amlogic.
      
      On the other side, the Amlogic G12A AFBC decoder seems to be an external
      IP that emit pixels on an AXI master hooked to a "Mali Unpack" block
      feeding the OSD1 VIU pixel input.
      This uses a weird "0x1000000" internal HW physical address on both
      sides to transfer the pixels.
      
      For Amlogic GXM, the supported pixel formats are the same as the normal
      linear OSD1 mode.
      
      On the other side, Amlogic added support for all AFBC v1.2 formats for
      the G12A AFBC integration.
      
      For simplicity, we stick to the already supported formats for now.
      Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
      Reviewed-by: default avatarKevin Hilman <khilman@baylibre.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20191021091509.3864-7-narmstrong@baylibre.com
      68e2f64e
    • Neil Armstrong's avatar
      drm/meson: Add AFBCD module driver · d1b5e41e
      Neil Armstrong authored
      This adds the driver for the ARM Framebuffer Compression decoders found
      in the Amlogic GXM and G12A SoCs.
      
      The Amlogic GXM and G12A AFBC decoder are totally different, the GXM only
      handling only the AFBC v1.0 modes and the G12A decoder handling the
      AFBC v1.2 modes.
      
      The G12A AFBC decoder is an external IP integrated in the video pipeline,
      and the GXM AFBC decoder seems to the an Amlogic custom decoder more
      tighly integrated in the video pipeline.
      
      The GXM AFBC decoder can handle only one AFBC plane for 2 available
      OSD planes available in HW, and the G12A AFBC decoder can handle up
      to 4 AFBC planes for up to 3 OSD planes available in HW.
      
      The Amlogic GXM supports 16x16 SPARSE and 16x16 SPLIT AFBC buffers up
      to 4k.
      
      On the other side, for G12A SPLIT is mandatory in 16x16 block mode, but
      for 4k modes 32x8+SPLIT AFBC buffers is manadatory for performances reasons.
      
      The RDMA is used here to reset and program the AFBC decoder unit
      on each vsync without involving the interrupt handler that can
      be masked for a long period of time, producing display glitches.
      
      For this we use the meson_rdma_writel_sync() which adds the register
      write tuple (VPU register offset and register value) to the RDMA buffer
      and write the value to the HW.
      
      When enabled, the RDMA is enabled to rewrite the same sequence at the
      next VSYNC event, until a new buffer is committed to the OSD plane.
      
      Then the Amlogic G12A is switched to RDMA, the Amlogic GXM Decoder
      doesn't need a reset/reprogram at each vsync, but needs to keep the
      vsync interrupt enabled to trigger the RDMA module.
      Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
      Reviewed-by: default avatarKevin Hilman <khilman@baylibre.com>
      [narmstrong: fixed typo in commit log]
      Link: https://patchwork.freedesktop.org/patch/msgid/20191021091509.3864-6-narmstrong@baylibre.com
      d1b5e41e
    • Neil Armstrong's avatar
      drm/meson: add RDMA module driver · 63fba242
      Neil Armstrong authored
      The VPU embeds a "Register DMA" that can write a sequence of registers
      on the VPU AHB bus, either manually or triggered by an internal IRQ
      event like VSYNC or a line input counter.
      
      The initial implementation handles a single channel (over 8), triggered
      by the VSYNC irq and does not handle the RDMA irq.
      
      The RDMA will be usefull to reset and program the AFBC decoder unit
      on each vsync without involving the interrupt handler that can
      be masked for a log period of time, producing display glitches.
      Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
      Reviewed-by: default avatarKevin Hilman <khilman@baylibre.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20191021091509.3864-5-narmstrong@baylibre.com
      63fba242
    • Neil Armstrong's avatar
      drm/meson: store the framebuffer width for plane commit · ce7cb472
      Neil Armstrong authored
      Also store the framebuffer width in the private common struct
      to be used by the AFBC decoder module driver when committing the AFBC
      plane.
      Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
      Reviewed-by: default avatarKevin Hilman <khilman@baylibre.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20191021091509.3864-4-narmstrong@baylibre.com
      ce7cb472
    • Neil Armstrong's avatar
      drm/meson: add RDMA register bits defines · 7704ddc6
      Neil Armstrong authored
      The Amlogic VPU embeds a "Register DMA" that can write a sequence of registers
      on the VPU AHB bus, either manually or triggered by an internal IRQ event like
      VSYNC or a line input counter.
      
      This adds the register defines.
      Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
      Reviewed-by: default avatarKevin Hilman <khilman@baylibre.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20191021091509.3864-3-narmstrong@baylibre.com
      7704ddc6
    • Neil Armstrong's avatar
      drm/meson: add AFBC decoder registers for GXM and G12A · 26a7abd4
      Neil Armstrong authored
      Add the registers used to program the ARM Framebuffer Compression decoders
      used in the Amlogic GXM and G12A SoCs families.
      
      This also adds the routing and pipeline configuration bits and registers
      needed to enable AFBC support.
      Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
      Reviewed-by: default avatarKevin Hilman <khilman@baylibre.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20191021091509.3864-2-narmstrong@baylibre.com
      26a7abd4
    • Jani Nikula's avatar
      samples: vfio-mdev: constify fb ops · b0077e52
      Jani Nikula authored
      Now that the fbops member of struct fb_info is const, we can start
      making the ops const as well.
      
      v2: fix typo (Christophe de Dinechin)
      
      Cc: Kirti Wankhede <kwankhede@nvidia.com>
      Cc: kvm@vger.kernel.org
      Reviewed-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      Acked-by: default avatarKirti Wankhede <kwankhede@nvidia.com>
      Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/ddb10df1316ef585930cda7718643a580f4fe37b.1575390741.git.jani.nikula@intel.com
      b0077e52
  2. 09 Dec, 2019 29 commits