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  1. 22 Oct, 2010 7 commits
    • Colin Cross's avatar
      [ARM] tegra: clock: Add dvfs support, bug fixes, and cleanups · 71fc84cc
      Colin Cross authored 
      - Add drivers to clock lookup table
- Add new pll_m entries
- Support I2C U16 divider
- Fix rate reporting on 32.768kHz clock
- Call propagate rate only if set_rate succeeds
- Add support for audio_sync clock
- Add 24MHz to PLLA frequency list
- Correct i2s1/2/spdifout mux
- Add suspend support
- Fix enable/disable parent clocks in set_parent
- Add max_rate parameter to all clocks
- DVFS support
- Add virtual cpu clock with dvfs
- Support clk_round_rate
- Fix requesting very high periph frequencies
- Add quirks for PLLU:
   PLLU is slightly different from the rest of the PLLs.  The
   lock enable bit is at bit 22 instead of 18 in the MISC
   register, and the post divider field is a single bit with
   reversed values from other PLLs.
- Simplify recalculating clock rates
- Fix UART divider flags
- Remove unused clock ops
Signed-off-by: default avatarColin Cross <ccross@android.com>
      71fc84cc
    • Colin Cross's avatar
      [ARM] tegra: Add support for reading fuses · 73625e3e
      Colin Cross authored 
      The Tegra SOC contains fuses to identify the CPU type and
bin, and a unique id.  The CPU info is required to determine
the correct voltages for each cpu and core frequency.
Signed-off-by: default avatarColin Cross <ccross@android.com>
      73625e3e
    • Colin Cross's avatar
      [ARM] tegra: gpio: Add suspend and wake support · 2e47b8b3
      Colin Cross authored 
      Includes checkpatch fixes and TEGRA_NR_GPIOS changes from
Mike Rapoport <mike@compulab.co.il>
Signed-off-by: default avatarColin Cross <ccross@android.com>
      2e47b8b3
    • Colin Cross's avatar
      [ARM] tegra: pinmux: add safe values, move tegra2, add suspend · c5f04b8d
      Colin Cross authored 
      - the reset values for some pin groups in the tegra pin mux can result in
functional errors due to conflicting with actively-configured pin groups
muxing from the same controller. this change adds a known safe, non-
conflicting mux for every pin group, which can be used on platforms
where the pin group is not routed to any peripheral

- also add each pin group's I/O voltage rail, to enable platform code to
map from the pin groups used by each interface to the regulators used
for dynamic voltage control

- add routines to individually configure the tristate, pin mux and pull-
ups for a pingroup_config array, so that it is possible to program
individual values at run-time without modifying other values.
this allows driver power-management code to reprogram individual
interfaces into lower power states during idle / suspend, or to
reprogram the pin mux to support multiple physical busses per
internal controller (e.g., sharing a single I2C or SPI controller
across multiple pin groups)

- move chip-specific data like pingroups and drive-pingroups
out of the common code and into chip-specific code

- fix debug output for group with no pullups

- add a TEGRA_MUX_SAFE function.  Setting a pingroup to TEGRA_MUX_SAFE
will automatically select a mux setting that is guaranteed not to
conflict with any of the hardware blocks.
Signed-off-by: default avatarGary King <gking@nvidia.com>
      c5f04b8d
    • Gary King's avatar
      [ARM] tegra: add suspend and mirror irqs to legacy controller · 460907bc
      Gary King authored 
      mirror IRQ enable and disable operations on the legacy PPI system
interrupt controller, since the legacy controller is responsible
for responding to wakeup interrupts when the CPU is in LP2 idle mode

save the irq controller state on suspend and restore on resume
Signed-off-by: default avatarGary King <gking@nvidia.com>
      460907bc
    • Colin Cross's avatar
      [ARM] tegra: Add legacy irq support · 8726e4f5
      Colin Cross authored 
      The "legacy irq controller" duplicates the functionality of the GIC,
but remains powered during the cpu suspend and idle modes that power
down the CPU and the GIC.
Signed-off-by: default avatarColin Cross <ccross@android.com>
      8726e4f5
    • Colin Cross's avatar
      [ARM] tegra: update iomap · c231d697
      Colin Cross authored 
      Add missing io address map entries from datasheet.
Add the IRAM area to the statically mapped io regions.
Correct the onewire, USB, and statmon addresses
Signed-off-by: default avatarColin Cross <ccross@android.com>
      c231d697
  3. 21 Oct, 2010 33 commits
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