- 03 Nov, 2015 4 commits
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Bjorn Helgaas authored
* pci/host-layerscape: PCI: layerscape: Add ls_pcie_msi_host_init() PCI: layerscape: Add support for LS1043a and LS2080a PCI: layerscape: Remove unused fields from struct ls_pcie PCI: layerscape: Update ls_add_pcie_port() PCI: layerscape: Factor out SCFG related function PCI: layerscape: Ignore PCIe controllers in Endpoint mode PCI: layerscape: Remove ls_pcie_establish_link()
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Bjorn Helgaas authored
* pci/host-hisi: PCI: hisi: Add HiSilicon SoC Hip05 PCIe driver
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Bjorn Helgaas authored
Merge branches 'pci/host-altera', 'pci/host-designware', 'pci/host-generic', 'pci/host-imx6', 'pci/host-iproc', 'pci/host-mvebu', 'pci/host-rcar', 'pci/host-tegra' and 'pci/host-xgene' into next * pci/host-altera: PCI: altera: Add Altera PCIe MSI driver PCI: altera: Add Altera PCIe host controller driver ARM: Add msi.h to Kbuild * pci/host-designware: PCI: designware: Make "clocks" and "clock-names" optional DT properties PCI: designware: Make driver arch-agnostic ARM/PCI: Replace pci_sys_data->align_resource with global function pointer PCI: designware: Use of_pci_get_host_bridge_resources() to parse DT Revert "PCI: designware: Program ATU with untranslated address" PCI: designware: Move calculation of bus addresses to DRA7xx PCI: designware: Make "num-lanes" an optional DT property PCI: designware: Require config accesses to be naturally aligned PCI: designware: Simplify dw_pcie_cfg_read/write() interfaces PCI: designware: Use exact access size in dw_pcie_cfg_read() PCI: spear: Fix dw_pcie_cfg_read/write() usage PCI: designware: Set up high part of MSI target address PCI: designware: Make get_msi_addr() return phys_addr_t, not u32 PCI: designware: Implement multivector MSI IRQ setup PCI: designware: Factor out MSI msg setup PCI: Add msi_controller setup_irqs() method for special multivector setup PCI: designware: Fix PORT_LOGIC_LINK_WIDTH_MASK * pci/host-generic: PCI: generic: Fix address window calculation for non-zero starting bus PCI: generic: Pass starting bus number to pci_scan_root_bus() PCI: generic: Allow multiple hosts with different map_bus() methods arm64: dts: Drop linux,pci-probe-only from the Seattle DTS powerpc/PCI: Fix lookup of linux,pci-probe-only property PCI: generic: Fix lookup of linux,pci-probe-only property of/pci: Add of_pci_check_probe_only to parse "linux,pci-probe-only" * pci/host-imx6: PCI: imx6: Add PCIE_PHY_RX_ASIC_OUT_VALID definition PCI: imx6: Return real error code from imx6_add_pcie_port() * pci/host-iproc: PCI: iproc: Fix header comment "Corporation" misspelling PCI: iproc: Add outbound mapping support PCI: iproc: Update PCIe device tree bindings PCI: iproc: Improve link detection logic PCI: iproc: Fix PCIe reset logic PCI: iproc: Call pci_fixup_irqs() for ARM64 as well as ARM PCI: iproc: Remove unused struct iproc_pcie.irqs[] PCI: iproc: Fix code comment to match code * pci/host-mvebu: PCI: mvebu: Remove code restricting accesses to slot 0 PCI: mvebu: Add PCI Express root complex capability block PCI: mvebu: Improve clock/reset handling PCI: mvebu: Use gpio_desc to carry around gpio PCI: mvebu: Use devm_kcalloc() to allocate an array PCI: mvebu: Use gpio_set_value_cansleep() PCI: mvebu: Split port parsing and resource claiming from port setup PCI: mvebu: Fix memory leaks and refcount leaks PCI: mvebu: Move port parsing and resource claiming to separate function PCI: mvebu: Use port->name rather than "PCIe%d.%d" PCI: mvebu: Report full node name when reporting a DT error PCI: mvebu: Use for_each_available_child_of_node() to walk child nodes PCI: mvebu: Use of_get_available_child_count() PCI: mvebu: Use exact config access size; don't read/modify/write PCI: mvebu: Return zero for reserved or unimplemented config space * pci/host-rcar: PCI: rcar: Fix I/O offset for multiple host bridges PCI: rcar: Set root bus nr to that provided in DT PCI: rcar: Remove dependency on ARM-specific struct hw_pci PCI: rcar: Make PCI aware of the I/O resources PCI: rcar: Build pcie-rcar.c only on ARM PCI: rcar: Build pci-rcar-gen2.c only on ARM * pci/host-tegra: PCI: tegra: Wrap static pgprot_t initializer with __pgprot() * pci/host-xgene: PCI/MSI: xgene: Remove msi_controller assignment
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Ley Foon Tan authored
Add Altera PCIe MSI driver. This soft IP supports a configurable number of vectors, which is a DTS parameter. [bhelgaas: Kconfig depend on PCIE_ALTERA, typos, whitespace] Signed-off-by:
Ley Foon Tan <lftan@altera.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com> Reviewed-by:
Marc Zyngier <marc.zyngier@arm.com> Acked-by:
Rob Herring <robh@kernel.org>
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- 02 Nov, 2015 21 commits
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Bjorn Helgaas authored
Merge branches 'pci/aer', 'pci/hotplug', 'pci/misc', 'pci/msi', 'pci/resource' and 'pci/virtualization' into next * pci/aer: PCI/AER: Clear error status registers during enumeration and restore * pci/hotplug: PCI: pciehp: Queue power work requests in dedicated function * pci/misc: PCI: Turn off Request Attributes to avoid Chelsio T5 Completion erratum x86/PCI: Make pci_subsys_init() static PCI: Add builtin_pci_driver() to avoid registration boilerplate PCI: Remove unnecessary "if" statement * pci/msi: x86/PCI: Don't alloc pcibios-irq when MSI is enabled PCI/MSI: Export all remapped MSIs to sysfs attributes PCI: Disable MSI on SiS 761 * pci/resource: sparc/PCI: Add mem64 resource parsing for root bus PCI: Expand Enhanced Allocation BAR output PCI: Make Enhanced Allocation bitmasks more obvious PCI: Handle Enhanced Allocation capability for SR-IOV devices PCI: Add support for Enhanced Allocation devices PCI: Add Enhanced Allocation register entries PCI: Handle IORESOURCE_PCI_FIXED when assigning resources PCI: Handle IORESOURCE_PCI_FIXED when sizing resources PCI: Clear IORESOURCE_UNSET when reverting to firmware-assigned address * pci/virtualization: PCI: Fix sriov_enable() error path for pcibios_enable_sriov() failures PCI: Wait 1 second between disabling VFs and clearing NumVFs PCI: Reorder pcibios_sriov_disable() PCI: Remove VFs in reverse order if virtfn_add() fails PCI: Remove redundant validation of SR-IOV offset/stride registers PCI: Set SR-IOV NumVFs to zero after enumeration PCI: Enable SR-IOV ARI Capable Hierarchy before reading TotalVFs PCI: Don't try to restore VF BARs
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Zhou Wang authored
Add PCIe host support for HiSilicon SoC Hip05, related DT binding documentation, and maintainer update. [bhelgaas: changelog, 32-bit only config write warning text] Signed-off-by:
Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by:
Gabriele Paoloni <gabriele.paoloni@huawei.com> Signed-off-by:
liudongdong <liudongdong3@huawei.com> Signed-off-by:
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Minghuan Lian authored
Layerscape PCIe has its own MSI implementation. Register ls_pcie_msi_host_init() to avoid using DesignWare's MSI. [bhelgaas: add comment] Signed-off-by:
Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by:
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Minghuan Lian authored
Both LS1043a and LS2080a are based on ARMv8 64-bit architecture and have similar PCIe implementation. LUT is added to controller. Add LS1043a and LS2080a support. [bhelgaas: move unused field removal into separate patch, include DT update] Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> (DT update) Signed-off-by:
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Minghuan Lian authored
Removed unused node, dev, and bus fields from struct ls_pcie. [bhelgaas: split into separate patch] Signed-off-by:
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Minghuan Lian authored
Update the ls_add_pcie_port() signature to keep it consistent with the other DesignWare-based host drivers. Signed-off-by:
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Minghuan Lian authored
For the LS1021a PCIe controller, some status registers are located in SCFG, unlike other Layerscape devices. Move SCFG-related code to ls1021_pcie_host_init() and rename ls_pcie_link_up() to ls1021_pcie_link_up() because LTSSM status is also in SCFG. Signed-off-by:
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Minghuan Lian authored
Layerscape PCIe controller supports root complex (RC) and endpoint (EP) modes, which can be set by RCW. If not in RC mode, return -ENODEV without claiming the controller. Signed-off-by:
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Minghuan Lian authored
ls_pcie_establish_link() does not do any real operation, except to wait for the linkup establishment. In fact, this is not necessary. Moreover, each PCIe controller not inserted device will increase the Linux startup time about 200ms. Remove ls_pcie_establish_link(). Signed-off-by:
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Bhupesh Sharma authored
Move the clock-related properties in the DesignWare PCIe controller bindings to 'optional' set of properties. [bhelgaas: move to separate patch] Signed-off-by:
Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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Zhou Wang authored
Previously, dw_pcie_host_init() created the PCI host bridge with pci_common_init_dev(), an ARM-specific function that supplies the ARM- specific pci_sys_data structure as the PCI "sysdata". Make pcie-designware.c arch-agnostic by reimplementing the functionality of pci_common_init_dev() directly in dw_pcie_host_init(). Note that this changes the bridge sysdata from the ARM pci_sys_data to the DesignWare pcie_port structure. This doesn't affect the ARM sysdata users because they are all specific to non-DesignWare host bridges, which will still have pci_sys_data. [bhelgaas: changelog] Tested-by:
James Morse <james.morse@arm.com> Tested-by:
Gabriel Fernandez <gabriel.fernandez@st.com> Tested-by:
Pratyush Anand <pratyush.anand@gmail.com>
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Gabriele Paoloni authored
dw_pcie_host_init() creates the PCI host bridge with pci_common_init_dev(), an ARM-specific function that supplies the ARM-specific pci_sys_data structure as the PCI "sysdata". To use dw_pcie_host_init() on other architectures, we will copy the internals of pci_common_init_dev() into pcie-designware.c instead of calling it, and dw_pcie_host_init() will supply the DesignWare pcie_port structure as "sysdata". Most ARM "sysdata" users are specific to non-DesignWare host bridges; they'll be unaffected because those bridges will continue to have the ARM pci_sys_data. Most of the rest are ARM-generic functions called by pci_common_init_dev(); these will be unaffected because dw_pcie_host_init() will no longer call pci_common_init(). But the ARM pcibios_align_resource() can be called by the PCI core for any bridge, so it can't depend on sysdata since it may be either pci_sys_data or pcie_port. Remove the pcibios_align_resource() dependency on sysdata by replacing the pci_sys_data->align_resource pointer with a global function pointer. This is less general (we can no longer have per-host bridge align_resource() methods), but the pci_sys_data->align_resource pointer was used only by Marvell (see mvebu_pcie_enable()), so this would only be a problem if we had a system with a combination of Marvell and other host bridges [bhelgaas: changelog] Signed-off-by:
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Zhou Wang authored
Use the new of_pci_get_host_bridge_resources() API in place of the PCI OF DT parser. [bhelgaas: changelog] Tested-by:
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Zhou Wang authored
Revert f4c55c5a ("PCI: designware: Program ATU with untranslated address"). Note that dra7xx_pcie_host_init() now modifies pp->io_base, but we still need the original value for dw_pcie_setup() in the path below, so this adds a new io_base_tmp member. It will be removed later when dw_pcie_setup() is removed. dra7xx_add_pcie_port dw_pcie_host_init pp->io_base = range.cpu_addr pp->io_base_tmp = range.cpu_addr # <-- added pp->ops->host_init dra7xx_pcie_host_init # ops->host_init pp->io_base &= DRA7XX_CPU_TO_BUS_ADDR # <-- modified pci_common_init_dev(..., &dw_pci) pcibios_init_hw hw->setup dw_pcie_setup # hw_pci.setup pci_ioremap_io(..., pp->io_base_tmp) # <-- original addr required [bhelgaas: changelog] Tested-by:
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Gabriele Paoloni authored
Commit f4c55c5a ("PCI: designware: Program ATU with untranslated address") added the calculation of PCI bus addresses in pcie-designware.c, storing them in new fields added in struct pcie_port. This calculation is done for every DesignWare user even though it only applies to DRA7xx. Move the calculation of the bus addresses to the DRA7xx driver to allow the rework of DesignWare to use the new DT parsing API. Signed-off-by:
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Gabriele Paoloni authored
Currently "num-lanes" is read in dw_pcie_host_init(), but it is only used if we call dw_pcie_setup_rc() while bringing up the link. If the link has already been brought up by firmware, we need not call dw_pcie_setup_rc(), and "num-lanes" is unnecessary. Only complain about "num-lanes" if we actually need it and we didn't find a valid value. [bhelgaas: changelog] Signed-off-by:
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Gabriele Paoloni authored
Add sanity checks on "addr" input parameter in dw_pcie_cfg_read() and dw_pcie_cfg_write(). These checks make sure that accesses are aligned on their size, e.g., a 4-byte config access is aligned on a 4-byte boundary. [bhelgaas: changelog, set *val = 0 in failure case] Signed-off-by:
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Gabriele Paoloni authored
Callers of dw_pcie_cfg_read() and dw_pcie_cfg_write() previously had to split the address into "addr" and "where". The callees assumed "addr" was 32-bit aligned (with zeros in the low two bits) and they used only the low two bits of "where". Accept the entire address in "addr" and drop the now-redundant "where" argument. As an example, this replaces this: int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val) *val = readb(addr + (where & 1)); with this: int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val) *val = readb(addr): [bhelgaas: changelog, split access size change to separate patch] Signed-off-by: -
Gabriele Paoloni authored
dw_pcie_cfg_write() uses the exact 8-, 16-, or 32-bit access size requested, but dw_pcie_cfg_read() previously performed a 32-bit read and masked out the bits requested. Use the exact access size in dw_pcie_cfg_read(). For example, if we want an 8-bit read, use readb() instead of using readl() and masking out the 8 bits we need. This makes it symmetric with dw_pcie_cfg_write(). [bhelgaas: split into separate patch, set *val = 0 in failure case] Signed-off-by:
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Gabriele Paoloni authored
The first argument of dw_pcie_cfg_read/write() is a 32-bit aligned address. The second argument is the byte offset into a 32-bit word, and dw_pcie_cfg_read/write() only look at the low two bits. SPEAr13xx used dw_pcie_cfg_read() and dw_pcie_cfg_write() incorrectly: it passed important address bits in the second argument, where they were ignored. Pass the complete 32-bit word address in the first argument and only the 2-bit offset into that word in the second argument. Without this fix, SPEAr13xx host will never work with few buggy gen1 card which connects with only gen1 host and also with any endpoint which would generate a read request of more than 128 bytes. [bhelgaas: changelog] Reported-by:
Pratyush Anand <panand@redhat.com> Signed-off-by:
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Lucas Stach authored
Set up the high part of the MSI target address to allow the MSI target to be above 4GB on 64bit and PAE systems. [bhelgaas: changelog] Signed-off-by:
Lucas Stach <l.stach@pengutronix.de> Signed-off-by:
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- 30 Oct, 2015 10 commits
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Alexander Duyck authored
Disable VFs if pcibios_enable_sriov() fails, just like we do for other errors in sriov_enable(). Call pcibios_sriov_disable() if virtfn_add() fails. [bhelgaas: changelog, split to separate patch for reviewability] Fixes: 995df527 ("PCI: Add pcibios_sriov_enable() and pcibios_sriov_disable()") Signed-off-by:
Alexander Duyck <aduyck@mirantis.com> Signed-off-by:
Wei Yang <weiyang@linux.vnet.ibm.com>
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Alexander Duyck authored
Per sec 3.3.3.1 of the SR-IOV spec, r1.1, we must allow 1.0s after clearing VF Enable before reading any field in the SR-IOV Extended Capability. Wait 1 second before calling pci_iov_set_numvfs(), which reads PCI_SRIOV_VF_OFFSET and PCI_SRIOV_VF_STRIDE after it sets PCI_SRIOV_NUM_VF. [bhelgaas: split to separate patch for reviewability, add spec reference] Signed-off-by:
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Alexander Duyck authored
Move pcibios_sriov_disable() up so it's defined before a future use. [bhelgaas: split to separate patch for reviewability] Signed-off-by:
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Alexander Duyck authored
If virtfn_add() fails, we call virtfn_remove() for any previously added devices. Remove the devices in reverse order (first-added is last-removed), which is more natural and doesn't require an additional variable. [bhelgaas: changelog, split to separate patch for reviewability] Signed-off-by:
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Phil Edworthy authored
Fix I/O offset for multiple host bridges. Signed-off-by:
Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Phil Edworthy authored
On ARM64, setting the root bus number to -1 causes probe failure. Moreover, we should use the bus number specified in the DT as we could have multiple PCIe controllers with different bus ranges. Signed-off-by:
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Phil Edworthy authored
The R-Car PCIe host controller driver uses pci_common_init_dev(), which is ARM-specific and requires the ARM struct hw_pci. The part of pci_common_init_dev() that is needed is limited and can be done here without using hw_pci. Note that the ARM pcibios functions expect the PCI sysdata to be a pointer to a struct pci_sys_data. Add a struct pci_sys_data as the first element in struct gen_pci so that when we use a gen_pci pointer as sysdata, it is also a pointer to a struct pci_sys_data. Create and scan the root bus directly without using the ARM pci_common_init_dev() interface. Based on 499733e0 ("PCI: generic: Remove dependency on ARM-specific struct hw_pci"). Signed-off-by:
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Phil Edworthy authored
Make PCI aware of the I/O resources. Signed-off-by:
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Geert Uytterhoeven authored
The pcie-rcar.c driver (controlled by PCI_RCAR_GEN2_PCIE) uses struct pci_sys_data and pci_ioremap_io(), which only exist on ARM. Building it on other arches, e.g., arm64/shmobile, causes errors like this: drivers/pci/host/pcie-rcar.c:138:52: warning: 'struct pci_sys_data' declared inside parameter list drivers/pci/host/pcie-rcar.c:380:4: error: implicit declaration of function 'pci_ioremap_io' [-Werror=implicit-function-declaration] Build pcie-rcar.c only on ARM. [bhelgaas: changelog, split to separate pci-rcar-gen2 from pcie-rcar] Reported-by: Wolfram Sang <wsa@the-dreams.de> (pci_ioremap_io()) Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
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Geert Uytterhoeven authored
The pci-rcar-gen2.c driver (controlled by PCI_RCAR_GEN2) uses struct pci_sys_data, which only exists on ARM. Building it on other arches, e.g., arm64/shmobile, causes errors like this: drivers/pci/host/pci-rcar-gen2.c: In function 'rcar_pci_cfg_base': drivers/pci/host/pci-rcar-gen2.c:112:34: error: dereferencing pointer to incomplete type struct rcar_pci_priv *priv = sys->private_data; ^ Build pci-rcar-gen2.c only on ARM. [bhelgaas: changelog, split to separate pci-rcar-gen2 from pcie-rcar] Signed-off-by:
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- 29 Oct, 2015 5 commits
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Yinghai Lu authored
David reported that a T5-8 sparc system failed to boot with: pci_sun4v f02dbcfc: PCI host bridge to bus 0000:00 pci_bus 0000:00: root bus resource [io 0x804000000000-0x80400fffffff] (bus address [0x0000-0xfffffff]) pci_bus 0000:00: root bus resource [mem 0x800000000000-0x80007effffff] (bus address [0x00000000-0x7effffff]) pci 0000:00:01.0: can't claim BAR 15 [mem 0x100000000-0x4afffffff pref]: no compatible bridge window Note that we don't know about a host bridge aperture that contains BAR 15. OF does report a MEM64 aperture, but before this patch, pci_determine_mem_io_space() ignored it. Add support for host bridge apertures with 64-bit PCI addresses. Also set IORESOURCE_MEM_64 for PCI device and bridge resources in PCI 64-bit memory space. Sparc doesn't actually print the device and bridge resources, but after this patch, we should have the equivalent of this: pci_sun4v f02dbcfc: PCI host bridge to bus 0000:00 pci_bus 0000:00: root bus resource [io 0x804000000000-0x80400fffffff] (bus address [0x0000-0xfffffff]) pci_bus 0000:00: root bus resource [mem 0x800000000000-0x80007effffff] (bus address [0x00000000-0x7effffff]) pci_bus 0000:00: root bus resource [mem 0x800100000000-0x8007ffffffff] (bus address [0x100000000-0x7ffffffff]) pci 0000:00:01.0: bridge window [mem 0x800100000000-0x8004afffffff 64bit pref] [bhelgaas: changelog, URL to David's report] Fixes: d63e2e1f ("sparc/PCI: Clip bridge windows to fit in upstream windows") Link: http://lkml.kernel.org/r/5514391F.2030300@oracle.comReported-by:
David Ahern <david.ahern@oracle.com> Tested-by:
Khalid Aziz <khalid.aziz@oracle.com> Signed-off-by:
Yinghai Lu <yinghai@kernel.org> Signed-off-by:
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Bjorn Helgaas authored
An Enhanced Allocation Capability entry with BEI 0 fills in dev->resource[0] just like a real BAR 0 would, but non-EA experts might not connect "EA - BEI 0" with BAR 0. Decode the EA jargon a little bit, e.g., change this: pci 0002:01:00.0: EA - BEI 0, Prop 0x00: [mem 0x84300000-0x84303fff] to this: pci 0002:01:00.0: BAR 0: [mem 0x84300000-0x84303fff] (from Enhanced Allocation, properties 0x00) Signed-off-by: -
Bjorn Helgaas authored
Expand bitmask #defines completely. This puts the shift in the code instead of in the #define, but it makes it more obvious in the header file how fields in the register are laid out. No functional change. Signed-off-by: -
David Daney authored
SR-IOV BARs can be specified via EA entries. Extend the EA parser to extract the SRIOV BAR resources, and modify sriov_init() to use resources previously obtained via EA. Signed-off-by:
David Daney <david.daney@cavium.com> Signed-off-by:
Sean O. Stalley <sean.stalley@intel.com>
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Sean O. Stalley authored
Add support for devices using Enhanced Allocation entries instead of BARs. This allows the kernel to parse the EA Extended Capability structure in PCI config space and claim the BAR-equivalent resources. See https://pcisig.com/sites/default/files/specification_documents/ECN_Enhanced_Allocation_23_Oct_2014_Final.pdf [bhelgaas: add spec URL, s/pci_ea_set_flags/pci_ea_flags/, consolidate declarations, print unknown property in hex to match spec] Signed-off-by:
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