Appears to be compatible with GK104.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

Appears to be compatible with TU104.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

No real surprised here so far.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

Appears to be compatible with GP100.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

RTX2070 appears to have 3 copies of the engine.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

Various different bits and pieces vs GV100.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

Appears to be compatible with GV100.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

Appears to be compatible with GP100.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

Appears to be compatible with GP102.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

New registers.

Currently uncertain how exactly to mask fault buffer interrupts.  This will
likely be corrected at around the same time as the new MC interrupt stuff
has been properly figured out and implemented.

For the moment, it shouldn't matter too much.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

New registers.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

New flush method.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

Appears to be compatible with GP102.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

Appears to be compatible with GV100.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

Appears to be compatible with NV50.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

Appears to be compatible with GK20A.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

Appears to be compatible with GF100.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

Things are a bit different here on Turing, and will require further changes
yet once I've investigated them more thoroughly.

For now though, the existing GP100 code is compatible enough with one small
hack to forward on fault buffer interrupts.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

Appears to be compatible with GM107.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

Appears to be compatible with GM200.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

Appears to be compatible with GK104.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

Appears to be compatible with GM200.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

Appears to be compatible with GK104.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

The GPU executes DEVINIT itself now, which makes our lives a bit easier.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

No real surprises here so far.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

Appears to be compatible with GP100.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

Will be required for Turing.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

The token will also contain runlist ID on Turing, so instead expose it as
an opaque value from NVKM so the client doesn't need to care.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

The GPU saves off some stuff to the address specified in this part of RAMFC
when the channel faults, so we should probably point it at a valid address.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

The trick we used (and still use for older GPUs) doesn't work on Turing.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

Turing will require different code.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

We're about to be adding more of them.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

We will need to bash different registers on Turing.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

Will be used by SVM code to allow direct (without going through MMU) memcpy
using the GPU copy engines.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>