- 11 Jan, 2023 29 commits
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Dmitry Baryshkov authored
Add includes for PMICs used on the SM8450-HDK. This makes GPIO blocks and thermal sensors available to the user of the platform. Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221217003349.546852-6-dmitry.baryshkov@linaro.org
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Vinod Koul authored
SM8450 HDK features bunch of PMICs, add the PMICs which we have already upstream files Signed-off-by:
Vinod Koul <vkoul@kernel.org> Reviewed-by:
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Dmitry Baryshkov authored
Add includes for PMICs used on the SM8450-HDK. This makes GPIO blocks and thermal sensors available to the user of the platform. Signed-off-by:
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Vinod Koul authored
SM8450 QRD features bunch of PMICs, add the PMICs which we have already upstream files Signed-off-by:
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Krzysztof Kozlowski authored
Underscores should not be used in node names (dtc with W=2 warns about them), so replace them with hyphens. In few places adjust the name to match other nodes (e.g. xxx-regulator). Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by:
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Owen Yang authored
Add DT for sc7280-herobrine-zombie with NVMe Signed-off-by:
Owen Yang <ecs.taipeikernel@gmail.com> Reviewed-by:
Douglas Anderson <dianders@chromium.org> Signed-off-by:
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Konrad Dybcio authored
Add a fallback CCI compatible, as required by bindings. Signed-off-by:
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Konrad Dybcio authored
Add a fallback CCI compatible, as required by bindings. Signed-off-by:
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Konrad Dybcio authored
Add a fallback CCI compatible, as required by bindings. Signed-off-by:
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Konrad Dybcio authored
Add a fallback CCI compatible, as required by bindings. Signed-off-by:
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Konrad Dybcio authored
As much as it hurts me, there is no FM radio chips on these devices. It seems to be present on Japanese models, but these are not available globally and differ in a few more ways anyway (such as a super high-tech NFC chip). Since it's the only subdevice of its I2C host bus, disable said bus to save some power. Signed-off-by:
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Konrad Dybcio authored
As much as it hurts me, there is no FM radio chips on these devices. It seems to be present on Japanese models, but these are not available globally and differ in a few more ways anyway (such as a super high-tech NFC chip). Since it's the only subdevice of its I2C host bus, disable said bus to save some power. Signed-off-by:
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Konrad Dybcio authored
As much as it hurts me, there is no FM radio chips on these devices. It seems to be present on Japanese models, but these are not available globally and differ in a few more ways anyway (such as a super high-tech NFC chip). Signed-off-by:
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Srinivasa Rao Mandadapu authored
Set a performance state for audio clks so that the minimally correct corner voltage is picked when audio is active. Signed-off-by:
Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Signed-off-by:
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Krzysztof Kozlowski authored
The Always On Subsystem (AOSS) QMP is not a power domain controller since commit 13578045 ("arm64: dts: qcom: sc7180: Use QMP property to control load state") and few others. In fact, it was never a power domain controller but rather control of power state of remote processors. This power state control is now handled differently, thus the AOSS QMP nodes do not have power-domain-cells: sc7280-idp.dtb: power-controller@c300000: '#power-domain-cells' is a required property From schema: Documentation/devicetree/bindings/power/power-domain.yaml AOSS QMP is an interface to the actuall AOSS subsystem responsible for some of power management functions, thus let's call the nodes as "power-management". Signed-off-by:
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Krzysztof Kozlowski authored
The SPMI bus uses two address cells and zero size cells (second reg entry - SPMI_USID - is not the size): spmi@c440000: #address-cells:0:0: 2 was expected Fixes: 152d1faf ("arm64: dts: qcom: add SC8280XP platform") Signed-off-by:
Stephen Boyd <swboyd@chromium.org> Reviewed-by:
Johan Hovold <johan+linaro@kernel.org> Signed-off-by:
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Krzysztof Kozlowski authored
The SPMI bus uses two address cells and zero size cells (second reg entry - SPMI_USID - is not the size): spmi@c440000: #address-cells:0:0: 2 was expected Fixes: 14abf8df ("arm64: dts: qcom: sc7280: Add SPMI PMIC arbiter device for SC7280") Signed-off-by:
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Krzysztof Kozlowski authored
The SPMI bus uses two address cells and zero size cells (second reg entry - SPMI_USID - is not the size): spmi@c440000: #address-cells:0:0: 2 was expected Fixes: 0f9dc5f0 ("arm64: dts: qcom: sc7180: Add SPMI PMIC arbiter device") Signed-off-by:
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Shazad Hussain authored
Add the pcie2a, pcie2a_phy, and respective tlmm nodes that are needed to get pcie 2a controller enabled on Qdrive3. This patch enables 4GB 64bit memory space for PCIE_2A to have BAR allocations of 64bit pref mem needed on this Qdrive3 platform with dual SoCs for root port and switch NT-EP. Hence this ranges property is overridden in sa8540p-ride.dts only. Moved tlmm node at the end as it tends to become rahter long. Link: https://lore.kernel.org/lkml/Y49k1k8ayI9%2FrK+R@hovoldconsulting.com/Signed-off-by:
Shazad Hussain <quic_shazhuss@quicinc.com> Reviewed-by:
Brian Masney <bmasney@redhat.com> Signed-off-by:
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Krzysztof Kozlowski authored
Order top-level nodes like memory, reserved-memory, opp-table-cpu alphabetically for easier code maintenance. No functional change (same dtx_diff, except phandle changes). Signed-off-by:
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Krzysztof Kozlowski authored
Order top-level nodes like memory, reserved-memory, opp-table-cpu alphabetically for easier code maintenance. No functional change (same dtx_diff). Signed-off-by:
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Rob Herring authored
'arm,kryo' is not documented and is not an Arm Ltd thing either as that is Qualcomm branding. The correct compatible is 'qcom,kryo'. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Konrad Dybcio authored
Nagara devices use the Dialog SLG51000 PMIC for powering some camera sensors. Add the required nodes to support it. Signed-off-by:
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Konrad Dybcio authored
Enable the power and volume up buttons, connected to PON and RESIN respectively. Signed-off-by:
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Konrad Dybcio authored
Set up gpio-controlled fixed regulators for camera on PDX223 and fix up the existing ones in common and PDX224 trees. Signed-off-by:
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Konrad Dybcio authored
With PMIC GPIOs now available, set up required pin settings and add gpio-keys. Signed-off-by:
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Konrad Dybcio authored
Sony ever so graciously provides GPIO line names in their downstream kernel (though sometimes they are not 100% accurate and you can judge that by simply looking at them and with what drivers they are used). Add these to the PDX223&224 DTSIs to better document the hardware. Diff between 223 and 224: pm8350b < "CAM_PWR_LD_EN", > "NC", pm8350c < "RGBC_IR_PWR_EN", > "NC", Which is due to different camera power wiring on 223 and lack of a ToF sensor on 224. Signed-off-by:
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Konrad Dybcio authored
Now that SPMI is finally in place, include the DTSIs of PMICs present on Nagara. Signed-off-by:
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Vinod Koul authored
Add the spmi bus as found in the SM8450 SoC Signed-off-by:
Konrad Dybcio <konrad.dybcio@somainline.org> [Konrad: 0x0 -> 0, move #cells down, make reg-names a vertical list] Signed-off-by:
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- 10 Jan, 2023 11 commits
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Neil Armstrong authored
Add the QCE and Crypto BAM DMA nodes. Signed-off-by:
Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by:
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Neil Armstrong authored
Add the I2C Master Hub wrapper and I2C serial engines nodes. Signed-off-by:
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Abel Vesa authored
Add dts file for Qualcomm MTP platform which uses SM8550 SoC. Co-developed-by:
Abel Vesa <abel.vesa@linaro.org> Reviewed-by:
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Neil Armstrong authored
Add nodes for PMR735d in separate dtsi file. Signed-off-by:
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Neil Armstrong authored
Add nodes for PMK8550 in separate dtsi file. Signed-off-by:
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Neil Armstrong authored
Add nodes for PM8550vs in separate dtsi file. Signed-off-by:
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Neil Armstrong authored
Add nodes for PM8550ve in separate dtsi file. Signed-off-by:
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Neil Armstrong authored
Add nodes for PM8550b in separate dtsi file. Signed-off-by:
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Neil Armstrong authored
Add nodes for PM8550 in separate dtsi file. Signed-off-by:
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Neil Armstrong authored
Add nodes for pm8010 in separate dtsi file. Signed-off-by:
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Abel Vesa authored
Add base dtsi for SM8550 SoC and includes base description of CPUs, GCC, RPMHCC, UART, interrupt controller, TLMM, reserved memory, RPMh PD, TCSRCC, ITS, IPCC, AOSS QMP, LLCC, cpufreq, interconnect, thermal sensor, cpu cooling maps and SMMU nodes which helps boot to shell with console on boards with this SoC. Co-developed-by:
Sai Prakash Ranjan <quic_saipraka@quicinc.com> Signed-off-by:
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