1. 10 Nov, 2017 4 commits
  2. 06 Nov, 2017 31 commits
  3. 02 Nov, 2017 5 commits
    • Thomas Gleixner's avatar
      Merge tag 'irqchip-4.15-2' of... · 722c908f
      Thomas Gleixner authored
      Merge tag 'irqchip-4.15-2' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core
      
      Pull the second batch of irqchip updates for 4.15 from marc Zyngier:
      
       - A number of MIPS GIC updates and cleanups
       - One GICv4 update
       - Another firmware workaround for GICv2
       - Support for Mason8 GPIOs
       - Tiny documentation fix
      722c908f
    • Paul Burton's avatar
      irqchip: mips-gic: Make IPI bitmaps static · 61dc367e
      Paul Burton authored
      We have 2 bitmaps used to keep track of interrupts dedicated to IPIs in
      the MIPS GIC irqchip driver. These bitmaps are only used from the one
      compilation unit of that driver, and so can be made static. Do so in
      order to avoid polluting the symbol table & global namespace.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: Jason Cooper <jason@lakedaemon.net>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: linux-mips@linux-mips.org
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      61dc367e
    • Paul Burton's avatar
      irqchip: mips-gic: Share register writes in gic_set_type() · 5af3e93e
      Paul Burton authored
      The gic_set_type() function included writes to the MIPS GIC polarity,
      trigger & dual-trigger registers in each case of a switch statement
      determining the IRQs type. This is all well & good when we only have a
      single cluster & thus a single GIC whose register we want to update. It
      will lead to significant duplication once we have multi-cluster support
      & multiple GICs to update.
      
      Refactor this such that we determine values for the polarity, trigger &
      dual-trigger registers and then have a single set of register writes
      following the switch statement. This will allow us to write the same
      values to each GIC in a multi-cluster system in a later patch, rather
      than needing to duplicate more register writes in each case.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: Jason Cooper <jason@lakedaemon.net>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: linux-mips@linux-mips.org
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      5af3e93e
    • Paul Burton's avatar
      irqchip: mips-gic: Remove gic_vpes variable · 82857688
      Paul Burton authored
      Following the past few patches nothing uses the gic_vpes variable any
      longer. Remove the dead code.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: Jason Cooper <jason@lakedaemon.net>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: linux-mips@linux-mips.org
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      82857688
    • Paul Burton's avatar
      irqchip: mips-gic: Use num_possible_cpus() to reserve IPIs · 25c51dad
      Paul Burton authored
      Reserving a number of IPIs based upon the number of VPs reported by the
      GIC makes little sense for a few reasons:
      
       - The kernel may have been configured with NR_CPUS less than the number
         of VPs in the cluster, in which case using gic_vpes causes us to
         reserve more interrupts for IPIs than we will possibly use.
      
       - If a kernel is configured without support for multi-threading & runs
         on a system with multi-threading & multiple VPs per core then we'll
         similarly reserve more interrupts for IPIs than we will possibly use.
      
       - In systems with multiple clusters the GIC can only provide us with
         the number of VPs in its cluster, not across all clusters. In this
         case we'll reserve fewer interrupts for IPIs than we need.
      
      Fix these issues by using num_possible_cpus() instead, which in all
      cases is actually indicative of how many IPIs we may need.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: Jason Cooper <jason@lakedaemon.net>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: linux-mips@linux-mips.org
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      25c51dad