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- 15 Jun, 2023 39 commits
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Nishanth Menon authored
MCU domain has it's own secure proxy for communicating with ROM and for R5 micro controller firmware operations. This is in addition to the one in the main domain NAVSS subsystem that is used for general purpose communication. Describe the node for use with bootloaders and firmware that require this communication path which uses interrupts to corresponding micro controller interrupt controller. Mark the node as disabled since this instance does not have interrupts routed to the main processor by default for a complete description of the node. Signed-off-by:
Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230530165900.47502-6-nm@ti.comSigned-off-by:
Vignesh Raghavendra <vigneshr@ti.com>
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Nishanth Menon authored
MCU domain has it's own secure proxy for communicating with ROM and for R5 micro controller firmware operations. This is in addition to the one in the main domain NAVSS subsystem that is used for general purpose communication. Describe the node for use with bootloaders and firmware that require this communication path which uses interrupts to corresponding micro controller interrupt controller. Mark the node as disabled since this instance does not have interrupts routed to the main processor by default for a complete description of the node. Signed-off-by:
Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20230530165900.47502-5-nm@ti.comSigned-off-by:
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Nishanth Menon authored
MCU domain has it's own secure proxy for communicating with ROM and for R5 micro controller firmware operations. This is in addition to the one in the main domain NAVSS subsystem that is used for general purpose communication. Describe the node for use with bootloaders and firmware that require this communication path which uses interrupts to corresponding micro controller interrupt controller. Mark the node as disabled since this instance does not have interrupts routed to the main processor by default for a complete description of the node. Signed-off-by:
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Nishanth Menon authored
Security Management Subsystem(SMS) has it's own unique secure proxy as part of Security Accelerator (SA3) module. This is used for communicating with ROM and for special usecases such as HSM operations. This is in addition to the one in the main domain DMSS subsystem that is used for general purpose communication. Describe the node for use with bootloaders and firmware that require this communication path which uses interrupts to corresponding micro controller interrupt controller. Mark the node as disabled since this instance does not have interrupts routed to the main processor by default for a complete description of the node. Signed-off-by:
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Nitin Yadav authored
Security Management Subsystem(SMS) has it's own unique secure proxy as part of Security Accelerator (SA3) module. This is used for communicating with ROM and for special usecases such as HSM operations. This is in addition to the one in the main domain DMSS subsystem that is used for general purpose communication. Describe the node for use with bootloaders and firmware that require this communication path which uses interrupts to corresponding micro controller interrupt controller. Mark the node as disabled since this instance does not have interrupts routed to the main processor by default for a complete description of the node. Signed-off-by:
Nitin Yadav <n-yadav@ti.com> [nm@ti.com: Update commit message, minor updates] Signed-off-by:
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Nishanth Menon authored
Just use "rtc" as the nodename to better match with the bindings. Signed-off-by:
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Nishanth Menon authored
ti,otap-del-sel has been deprecated in favor of ti,otap-del-sel-legacy. Drop the duplicate and misleading ti,otap-del-sel property. Signed-off-by:
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Nishanth Menon authored
s/mcan/can to stay in sync with bindings conventions. Signed-off-by:
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Vaishnav Achath authored
Describe OSPI flash partition information through device tree, this helps to remove passing partition information through the mtdparts commandline parameter which requires maintaining the partition information in a string format. AM64 SK and EVM has a S28 64 MiB OSPI flash with sector size of 256 KiB thus the size of the smallest partition is chosen as 256 KiB, the partition names and offsets are chosen according to the corresponding name and offsets in bootloader. Signed-off-by:
Vaishnav Achath <vaishnav.a@ti.com> Link: https://lore.kernel.org/r/20230513141712.27346-6-vaishnav.a@ti.comSigned-off-by:
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Vaishnav Achath authored
Describe OSPI flash partition information through device tree, this helps to remove passing partition information through the mtdparts commandline parameter which requires maintaining the partition information in a string format. AM654 baseboard has a MT35XU512ABA 64 MiB OSPI flash with sector size of 128 KiB thus the size of the smallest partition is chosen as 128 KiB, the partition names and offsets are chosen according to the corresponding name and offsets in bootloader. Signed-off-by:
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Vaishnav Achath authored
Describe OSPI and Hyperflash partition information through device tree, this helps to remove passing partition information through the mtdparts commandline parameter which requires maintaining the partition information in a string format. J7200 SoM has a S28 64 MiB OSPI flash with sector size of 256 KiB thus the size of the smallest partition is chosen as 256 KiB, the SoM also has a 64 MiB Hyperflash present on it, the partition names and offsets are chosen according to the corresponding name and offsets in bootloader. Signed-off-by:
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Vaishnav Achath authored
Describe OSPI flash partition information through device tree, this helps to remove passing partition information through the mtdparts commandline parameter which requires maintaining the partition information in a string format. J721E SK has a S28 64 MiB OSPI flash with sector size of 256 KiB thus the size of the smallest partition is chosen as 256 KiB, the partition names and offsets are chosen according to the corresponding name and offsets in bootloader. Signed-off-by:
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Vaishnav Achath authored
Describe OSPI and QSPI flash partition information through device tree, this helps to remove passing partition information through the mtdparts commandline parameter which requires maintaining the partition information in a string format. J721E SoM has a MT35 64 MiB OSPI flash and MT25 64 MiB QSPI flash both with sector size of 128 KiB thus the size of the smallest partition is chosen as 128KiB, the partition names and offsets are chosen according to the corresponding name and offsets in bootloader. Signed-off-by:
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Apurva Nandan authored
J784S4 has S28HS512T OSPI flash connected to OSPI0 and MT25QU512A QSPI flash connected to OSPI1, enable support for the same. Also describe the partition information according to the offsets in the bootloader. Co-developed-by:
Apurva Nandan <a-nandan@ti.com> Link: https://lore.kernel.org/r/20230504080305.38986-3-a-nandan@ti.comSigned-off-by:
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Apurva Nandan authored
TI K3 J784S4 has the Cadence OSPI controllers OSPI0 and OSPI1 on FSS bus for interfacing with OSPI flashes. Add the nodes to allow using SPI flashes. Signed-off-by:
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Wadim Egorov authored
With commit 9f6ffd0d ("dt-bindings: leds: Convert PCA9532 to dtschema"), we can now add the LED controller without introducing new dtbs_check warnings. Add missing I2C LED controller. Signed-off-by:
Wadim Egorov <w.egorov@phytec.de> Link: https://lore.kernel.org/r/20230505131012.2027309-1-w.egorov@phytec.deSigned-off-by:
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Vaishnav Achath authored
J721E common processor board has an onboard mux for selecting whether the OSPI signals are externally routed to OSPI flash or Hyperflash. The mux state signal input is tied to WKUP_GPIO0_8 and is used by bootloader for enabling the corresponding node accordingly. Add pinmux for the same. Signed-off-by:
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Vaishnav Achath authored
J7200 common processor board has an onboard mux for selecting whether the OSPI signals are externally routed to OSPI flash or Hyperflash. The mux state signal input is tied to WKUP_GPIO0_6 and is used by bootloader for enabling the corresponding node accordingly. Add pinmux for the same. Signed-off-by:
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Vaishnav Achath authored
J721E SoM has a HyperFlash and HyperRam connected to HyperBus memory controller, add corresponding node, pinmux and partitions for the same. HyperBus is muxed with OSPI and only one controller can be active at a time, therefore keep HyperBus node disabled. Bootloader will detect the external mux state through a wkup gpio and enable the node as required. Signed-off-by:
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Vaishnav Achath authored
J721E has a Flash SubSystem that has one OSPI and one HyperBus with muxed datapath and another independent OSPI. Add DT nodes for HyperBus controller and keep it disabled and model the data path selection mux as a reg-mux. Signed-off-by:
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Andrew Davis authored
MDIO nodes defined in the top-level J721e SoC dtsi files are incomplete and will not be functional unless they are extended with a pinmux. As the attached PHY is only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the MDIO nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by:
Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20230515172137.474626-5-afd@ti.comSigned-off-by:
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Andrew Davis authored
Mailbox nodes defined in the top-level AM64x SoC dtsi files are incomplete and may not be functional unless they are extended with a chosen interrupt and connection to a remote processor. As the remote processors depend on memory nodes which are only known at the board integration level, these nodes should only be enabled when provided with the above information. Disable the Mailbox nodes in the dtsi files and only enable the ones that are actually used on a given board. Signed-off-by:
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Andrew Davis authored
PCIe nodes defined in the top-level J721e SoC dtsi files are incomplete and will not be functional unless they are extended with a SerDes PHY. And usually only one of the two modes can be used at a time as they share a SerDes link. As the PHY and mode is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the PCIe nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by:
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Andrew Davis authored
These nodes are example nodes for the PCIe controller in "endpoint" mode. By default the controller is in "root complex" mode and there is already a DT node for the same. Examples should go in the bindings or other documentation. Remove this node. Signed-off-by:
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Andrew Davis authored
Mailbox nodes are now disabled by default. The BeagleBoard AI64 DT addition went in at around the same time and must have missed that change so the mailboxes are not re-enabled. Do that here. Fixes: fae14a1c ("arm64: dts: ti: Add k3-j721e-beagleboneai64") Signed-off-by:
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Bhavya Kapoor authored
eMMC tuning was incomplete earlier, so support for high speed modes was kept disabled. Remove no-1-8-v property to enable support for high speed modes for eMMC in J784S4 SoC. Signed-off-by:
Bhavya Kapoor <b-kapoor@ti.com> Link: https://lore.kernel.org/r/20230502090814.144791-1-b-kapoor@ti.comSigned-off-by:
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Bhavya Kapoor authored
J784S4 has two instances of 8 channel ADCs in MCU domain. Add pinmux information for both ADC nodes. Signed-off-by:
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Bhavya Kapoor authored
J784S4 has two instances of 8 channel ADCs in MCU domain. Add support for both ADC nodes. Signed-off-by:
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Jyri Sarha authored
The OLDI-LCD1EVM add on board has Rocktech RK101II01D-CT panel[1] with integrated touch screen. The integrated touch screen is Goodix GT928. This panel connects with AM65 GP-EVM[2]. Add DT nodes for these and connect the endpoint nodes with DSS. [1]: Panel link https://www.digimax.it/en/tft-lcd/20881-RK101II01D-CT [2]: AM654 LCD EVM: https://www.ti.com/tool/TMDSLCD1EVMSigned-off-by:
Jyri Sarha <jsarha@ti.com> Signed-off-by:
Nikhil Devshatwar <nikhil.nd@ti.com> [abhatia1@ti.com: Make cosmetic and 6.4 kernel DTSO syntax changes] Signed-off-by:
Aradhya Bhatia <a-bhatia1@ti.com> Reviewed-by:
Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Reviewed-by:
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Bhavya Kapoor authored
Update the delay values for various speed modes supported, based on the revised august 2021 J721E Datasheet. [1] - Table 7-77. MMC0 DLL Delay Mapping for All Timing Modes and Table 7-86. MMC1/2 DLL Delay Mapping for All Timing Modes, in https://www.ti.com/lit/ds/symlink/tda4vm.pdf, (SPRSP36J – FEBRUARY 2019 – REVISED AUGUST 2021) Signed-off-by:
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Nishanth Menon authored
Include documentation of the AMC package pin name as well to keep it consistent with the rest of the pinctrl documentation. Signed-off-by:
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Nishanth Menon authored
Add board EEPROM support to device tree Signed-off-by:
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Nishanth Menon authored
wkup_uart and main_uart1 on this platform is used by tifs and DM firmwares. Describe them for completeness including the pinmux. Signed-off-by:
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Nishanth Menon authored
Drop an extra EoL Signed-off-by:
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Nishanth Menon authored
Looks like a couple of http:// links crept in. Use https instead. While at it, drop unicode encoded character. Signed-off-by:
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Keerthy authored
VTM stands for Voltage Thermal Management. Add the thermal zones. Six sensors mapping to six thermal zones. Main0, Main1, Main2, Main3, WKUP1 & WKUP2 domains respectively. Signed-off-by:
Keerthy <j-keerthy@ti.com> [bb@ti.com: rebased on v6.3-rc1] Signed-off-by:
Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20230405215328.3755561-8-bb@ti.comSigned-off-by:
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Keerthy authored
VTM stands for Voltage Thermal Management. Add the thermal zones. Three sensors mapping to 3 thermal zones. MCU, MPU & Main domains respectively. Signed-off-by:
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Keerthy authored
VTM stands for Voltage Thermal Management. Add the thermal zones. Five sensors mapping ton 5 thermal zones. WKUP, MPU, C7x, GPU & R5F respectively. Signed-off-by:
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Keerthy authored
VTM stands for Voltage Thermal Management. Add the thermal zones. Seven sensors mapping to seven thermal zones. Main0, Main1, Main2, Main3, Main4, WKUP1 & WKUP2 domains respectively. Signed-off-by:
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- 14 Jun, 2023 1 commit
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Bryan Brattlof authored
The am62ax supports a single Voltage and Thermal Management (VTM) device located in the wakeup domain with three associated temperature monitors located in various hot spots of the die. Signed-off-by:
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