- 10 Jun, 2015 6 commits
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Shawn Guo authored
Update my mailbox to use kernel.org one for handling kernel community maintenance traffic. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org> Signed-off-by:
Kevin Hilman <khilman@linaro.org>
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Kevin Hilman authored
Merge tag 'imx-soc-4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/soc The i.MX SoC updates for 4.2: - Add new SoC i.MX7D support, which integrates two Cortex-A7 and one Cortex-M4 cores. - Support suspend from IRAM on i.MX53, so that DDR pins can be set to high impedance for more power saving during suspend. - Move i.MX clock drivers from arch/arm/mach-imx to drivers/clk/imx. - Move i.MX GPT timer driver from arch/arm/mach-imx into drivers/clocksource. - A couple of clock driver update for VF610 and i.MX6Q. - A few random code correction and improvement. * tag 'imx-soc-4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (44 commits) ARM: imx: imx7d requires anatop clocksource: timer-imx-gpt: remove include of <asm/mach/time.h> ARM: imx: move timer driver into drivers/clocksource ARM: imx: remove platform headers from timer driver ARM: imx: provide gpt device specific irq functions ARM: imx: get rid of variable timer_base ARM: imx: define gpt register offset per device type ARM: imx: move clock event variables into imx_timer ARM: imx: set up .set_next_event hook via imx_gpt_data ARM: imx: setup tctl register in device specific function ARM: imx: initialize gpt device type for DT boot ARM: imx: define an enum for gpt timer device type ARM: imx: move timer resources into a structure ARM: imx: use relaxed IO accessor in timer driver ARM: imx: make imx51/3 suspend optional ARM: clk-imx6q: refine sata's parent ARM: imx: clk-v610: Add clock for I2C2 and I2C3 ARM: mach-imx: iomux-imx31: Use DECLARE_BITMAP ARM: imx: add imx7d clk tree support ARM: clk: imx: update pllv3 to support imx7 ... Conflicts: arch/arm/mach-imx/Kconfig
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Kevin Hilman authored
* socfpga/soc: ARM: socfpga: support suspend to ram ARM: socfpga: add CPU_METHOD_OF_DECLARE for Arria 10 ARM: socfpga: use CPU_METHOD_OF_DECLARE for socfpga_cyclone5
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Alan Tull authored
Add code that requests that the sdr controller go into self-refresh mode. This code is run from ocram. Suspend-to-RAM and EDAC support are mutually exclusive on SOCFPGA. If the EDAC is enabled, it will prevent the platform from going into suspend. Example of how to request to suspend to ram: $ echo enabled > \ /sys/devices/soc/ffc02000.serial0/tty/ttyS0/power/wakeup $ echo -n mem > /sys/power/state Signed-off-by:
Alan Tull <atull@opensource.altera.com> Signed-off-by:
Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by:
Kevin Hilman <khilman@linaro.org>
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Dinh Nguyen authored
Add boot_secondary implementation for the Arria10 platform. Bringing up the secondary core on the Arria 10 platform is pretty similar to the Cyclone/Arria 5 platform, with the exception of the following differences: - Register offset to bringup CPU1 out of reset is different. - The cpu1-start-addr for Arria10 contains an additional nibble. Signed-off-by:
Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by:
Kevin Hilman <khilman@linaro.org>
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Dinh Nguyen authored
Convert cyclone5/arria5 to use CPU_METHOD_OF_DECLARE for smp operations. Signed-off-by:
Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by:
Kevin Hilman <khilman@linaro.org>
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- 03 Jun, 2015 34 commits
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Arnd Bergmann authored
Like i.MX6, the i.MX7 code calls into the anatop driver, which fails if that is disabled: arch/arm/mach-imx/built-in.o: In function `imx7d_init_machine': arch/arm/mach-imx/mach-imx7d.c:24: undefined reference to `imx_anatop_init' arch/arm/mach-imx/built-in.o: In function `imx7d_init_irq': arch/arm/mach-imx/mach-imx7d.c:29: undefined reference to `imx_init_revision_from_anatop' This patch ensures that for an imx7-only build, we still get anatop built-in, matching what we do for imx6. We also need to select HAVE_IMX_MMDC, as that is needed by the anatop code. Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Shawn Guo authored
The include of <asm/mach/time.h> is not needed at all, and causes build error in some cases. Remove it. Reported-by:
Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org> Acked-by:
Daniel Lezcano <daniel.lezcano@linaro.org>
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Shawn Guo authored
After the cleanup on imx timer driver, now it's ready to be moved into drivers/clocksource/. Let's do it. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org> Acked-by:
Daniel Lezcano <daniel.lezcano@linaro.org>
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Shawn Guo authored
With the cleanup done before, the platform specific headers now can be removed. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Shawn Guo authored
It splits irq enable/disable/acknowledge operations into device specific functions as the hooks in imx_gpt_data, so that we can save the use of timer_is_xxx() and cpu_is_xxx() checking in these irq functions. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Shawn Guo authored
We now have pointer to imx_timer structure available where timer base address is needed, so we can just kill global timer_base by using imxtm->base instead. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Shawn Guo authored
It defines offset of gpt registers TSTAT, TCN and TCMP per device type in imx_gpt_data, so that these registers can be accessed in an way without timer_is_v2() checking. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Shawn Guo authored
Since we now have imx_timer structure, it makes more sense to move those clock event related variables into the structure, so that we can save some global variables. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Shawn Guo authored
Set up .set_next_event hook via imx_gpt_data, so that we can save the use of timer_is_v2(). Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Shawn Guo authored
It creates a gpt device speicific data structure and adds function hook gpt_setup_tctl in there to set up gpt TCTL register. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Shawn Guo authored
Use different initialization function in CLOCKSOURCE_OF_DECLARE() to initialize gpt device type for DT boot. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Shawn Guo authored
Define an enum for gpt timer device type in include/soc/imx/timer.h to tell the gpt block differences among SoCs. Update non-DT users (clock drivers) to pass the device type. As we now have include/soc/imx/timer.h, the declaration of mxc_timer_init() is moved into there as the best fit. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Shawn Guo authored
Instead of passing around as individual argument, let's move timer resources like irq and clocks together with base address into a data structure, and pass pointer of the structure as argument to simplify the function call interface. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Shawn Guo authored
Replace the __raw_readl/__raw_writel with readl_relaxed/writel_relaxed which is endian-safe, as a step of moving the driver code into folder drivers/clocksource. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Arnd Bergmann authored
A recent change to the imx53 power management caused a build regression when CONFIG_SOC_IMX53 is disabled: mach-imx/built-in.o:(.init.rodata+0x60): undefined reference to `imx53_suspend' mach-imx/built-in.o:(.init.rodata+0x64): undefined reference to `imx53_suspend_sz' This avoids the problem by compiling the code in question conditionally on the presence of CONFIG_SOC_IMX53. For consistency, I'm also changing the same thing for CONFIG_SOC_IMX51. An additional benefit of this approach is reduced code size for kernels that only include support for one of the two SoCs. Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Fixes: 1579c7b9 ("ARM: imx53: Set DDR pins to high impedance when in suspend to RAM.") Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Sébastien Szymanski authored
According to IMX6D/Q RM, table 18-3, sata clock's parent is ahb, not ipg. Signed-off-by:
Sébastien Szymanski <sebastien.szymanski@armadeus.com> Reviewed-by:
Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Mirza Krak authored
Add support for clock gating of I2C2 and I2C3. We use I2C2 in a (not yet mainlined) device tree. Signed-off-by:
Mirza Krak <mirza.krak@hostmobility.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Joe Perches authored
Use the generic mechanism to declare a bitmap instead of unsigned long. Signed-off-by:
Joe Perches <joe@perches.com> Acked-by:
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Frank Li authored
Add i.MX7D clk tree support. Enable all clock to bring up imx7. Clock framework need be modified a little since imx7d change clock design. otherwise system will halt and block the other part upstream. All clock refine need wait for Dong Aisheng's patch clk: support clocks which requires parent clock on during operation Or other solution ready. Signed-off-by:
Anson Huang <b20788@freescale.com> Signed-off-by:
Adrian Alonso <aalonso@freescale.com> Signed-off-by:
Frank Li <Frank.Li@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Frank Li authored
Add type IMX_PLLV3_ENET_IMX7 Signed-off-by:
Frank Li <Frank.Li@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Stefan Agner authored
Enabled DAP (debug access port) by default. This enables the hw- breakpoint framework to make use of the breakpoints and watchpoints supported by hardware. [ 0.215805] hw-breakpoint: found 2 (+1 reserved) breakpoint and 1 watchpoint registers. [ 0.224624] hw-breakpoint: maximum watchpoint size is 4 bytes. Without this clock, the hw-breakpoint driver claims an undefined instruction during initialization: [ 0.227380] hw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 0 [ 0.227519] hw-breakpoint: CPU 0 failed to disable vector catch Signed-off-by:
Stefan Agner <stefan@agner.ch> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Martin Fuzzey authored
In order to save power the DDR pins should be put into high impedance when in suspend to RAM. This requires manually requesting self refresh (rather than using the automatic mode implemented by the CCM / ESDCTL), followed by reconfiguring the IOMUXC. Of course the code to do this cannot itself run from DDR so the code is copied to and executed from internal memory. In my tests using a custom i.MX53 board with LPDDR2 RAM this reduced the suspend power consumption from 200mW to 60mW. Signed-off-by:
Martin Fuzzey <mfuzzey@parkeon.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Anson Huang authored
Add i.MX7D MSL support. Signed-off-by:
Anson Huang <b20788@freescale.com> Signed-off-by:
Frank Li <Frank.Li@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Anson Huang authored
Add low level uart debug support for imx7d Signed-off-by:
Frank Li <Frank.Li@freescale.com> Signed-off-by:
Bai Ping <b51503@freescale.com> Signed-off-by:
Anson Huang <b20788@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Fabio Estevam authored
Include the "common.h" header file to fix the following sparse warning: arch/arm/mach-imx/mmdc.c:66:5: warning: symbol 'imx_mmdc_get_ddr_type' was not declared. Should it be static? Signed-off-by:
Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Fabio Estevam authored
Include the "clk.h" header file to fix the following sparse warning: drivers/clk/imx/clk-cpu.c:77:12: warning: symbol 'imx_clk_cpu' was not declared. Should it be static? Signed-off-by:
Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Shenwei Wang authored
The comments were corrected as the following to reflect the real situation of Freescale MXC timer IP block. There are totally 4 version of the timer on Freescale i.MX SoCs. Signed-off-by:
Shenwei Wang <shenwei.wang@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Shenwei Wang authored
Removed the duplicated function declaration of mxc_timer_init which was already declared in drivers/clk/imx/clk.h. Signed-off-by:
Shenwei Wang <shenwei.wang@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Krzysztof Kozlowski authored
The irq_domain_ops are not modified by the driver and the irqdomain core code accepts pointer to a const data. Signed-off-by:
Krzysztof Kozlowski <k.kozlowski.k@gmail.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Anson Huang authored
The definition of do_div uses unsigned long long variable as its first parameter, better to pass a u64 variable as first parameter when calling do_div function. Signed-off-by:
Anson Huang <b20788@freescale.com> Acked-by:
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Shawn Guo authored
Commit 4631960d26da ("ARM: imx6: set initial power mode in pm function") moves imx6_set_lpm() from clock init function into imx6_pm_common_init(). This causes a hang when cpuidle support is enabled. The reason for that is ARM core clock is shut down unexpectedly by WAIT mode. It happens with the following call stack: cpuidle_register_governor() cpuidle_switch_governor() cpuidle_uninstall_idle_handler() synchronize_sched() wait_rcu_gp() wait_for_completion() When wait_for_completion() is called as above, all cores are idle/WFI. Hence, the reset value of CCM_CLPCR_LPM - WAIT mode, will trigger a hardware shutdown of the ARM core clock. To fix the regression, we need to ensure that CCM_CLPCR_LPM is initialized into RUN mode earlier than cpuidle governor registration, which is a postcore_initcall. This patch creates function imx6_pm_ccm_init() to map CCM block and initialize CCM_CLPCR_LPM into RUN mode, and have the function called from machine .init_irq hook, which should be early enough. Reported-by:
Kevin Hilman <khilman@kernel.org> Fixes: 8fb76a07 ("ARM: imx6: set initial power mode in pm function") Tested-by:
Kevin Hilman <khilman@linaro.org> Tested-by:
Tyler Baker <tyler.baker@linaro.org> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Shawn Guo authored
EPIT provides another timer implementation besides the default GPT timer. The imx35 clock driver will use EPIT timer when option CONFIG_MXC_USE_EPIT is enabled. However, initializing timers from clock driver is a workaround solution and causes problem when we move clock drivers into driver/clk. Let's simply drop the EPIT initialization from there. If people really want this EPIT option, EPIT timer driver needs to be reworked to do the initialization in a standard way - use CLOCKSOURCE_OF_DECLARE() with device tree support. Reported-by:
kbuild test robot <fengguang.wu@intel.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Shawn Guo authored
Add new created folders drivers/clk/imx/ and include/soc/imx/ into IMX entry. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Shawn Guo authored
After the cleanup on clock drivers, they are now ready to be moved into drivers/clk. Let's move them into drivers/clk/imx folder. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org> Acked-by:
Stephen Boyd <sboyd@codeaurora.org>
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