- 07 Apr, 2015 34 commits
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Maciej W. Rozycki authored
Correct a cache coherency regression introduced with be1664c4 [Another round of fixes for the fp emulator.] for the emulation frame used in delay-slot emulation. Two instructions are copied into the frame and as from the commit referred a cache synchronisation call is made for the second instruction aka `badinst' of the two only. The `flush_cache_sigtramp' interface is reused that guarantees that synchronisation will be made for 8 bytes or 2 instructions starting from the address requested, although if cache lines are wider then a larger area may be synchronised. Change the call to point to the first of the two instructions aka `emul' instead, removing unpredictable behaviour resulting from cache incoherency. This bug only ever manifested itself on systems implementing 4-byte cache lines, typically MIPS I systems, causing all kinds of weirdness. This is because the sequence of two instructions starting from `emul' is 8-byte aligned and for 8-byte or wider cache lines the line synchronised will span both, so the vast majority of systems have escaped unharmed. Signed-off-by:
Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9698/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Maciej W. Rozycki authored
Do not lose the other half of the BREAK code where there is an upper half. This is so that e.g. `BREAK 7, 7' is not interpreted as a divide by zero trap, while `BREAK 0, 7' or `BREAK 7, 0' still are. Signed-off-by:
Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9697/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Maciej W. Rozycki authored
Add the missing microMIPS BREAK16 instruction code interpretation and reshape code removing instruction fetching duplication and the separate call to `do_trap_or_bp' in the MIPS16 path. Signed-off-by:
Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9696/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Maciej W. Rozycki authored
Correct the interpretation of the immediate MIPS16 BREAK instruction code embedded in the instruction word across bits 10:5 rather than 11:6 as current code implies, fixing the interpretation of integer overflow and divide by zero traps. Signed-off-by:
Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9695/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Maciej W. Rozycki authored
The `cpu_has_fpu' feature flag must not be hardcoded to 1 or the `nofpu' kernel option will be ignored. Remove any such overrides and add a cautionary note. Hardcoding to 0 is fine for FPU-less platforms. Signed-off-by:
Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9694/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Maciej W. Rozycki authored
The `ieee754sp_isnan' and `ieee754dp_isnan' NaN classifiers are now no longer externally referred, remove their header prototypes and make them local to the two only respective places still making use of them. Signed-off-by:
Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9693/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Maciej W. Rozycki authored
Rewrite qNaN handling in `ieee754sp_fdp' using the `ieee754_class_nan' helper recently added, removing the external call to `ieee754sp_isnan' and reducing the size of code by 16 instructions or 64 bytes. Signed-off-by:
Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9692/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Maciej W. Rozycki authored
None of the comparison helpers in ieee754.h is used, remove them. Signed-off-by:
Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9691/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Maciej W. Rozycki authored
Remove a redundant call to `ieee754_setandtestcx' in `ieee754sp_cmp' and `ieee754dp_cmp'. The IEEE 754 exception requested will have already been set by a call to `ieee754_setcx' immediately above, because `sig' has to be non-zero to reach here, and the comparison result returned will be 0 regardless of the result from the call. Simplify the return expression remaining. All this reducing the size of code by 16 and 12 instructions or 64 and 48 bytes respectively. Signed-off-by:
Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9690/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Maciej W. Rozycki authored
We have the input operands already classified in `ieee754sp_cmp' and `ieee754dp_cmp' comparison operations, so use the class obtained to tell NaNs and numbers apart rather than classifying inputs again for this purpose, reducing the size of code by 24 and 40 instructions or 96 and 160 bytes respectively. Signed-off-by:
Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9689/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Maciej W. Rozycki authored
Revert the changes made by commit fdffbafb [Lots of FPU bug fixes from Kjeld Borch Egevang.] to `ieee754sp_nanxcpt' and `ieee754dp_nanxcpt' sNaN quieting handlers and their callers so that sNaN processing is done within the handlers againg. Pass the sNaN causing an IEEE 754 invalid operation exception down to the relevant handler. Pass the sNaN in `fs' where two sNaNs are supplied to a binary operation. Set the Invalid Operation FCSR exception bits in the quieting handlers rather than at their call sites throughout. Make the handlers exclusive for sNaN processing. Signed-off-by:
Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9688/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Maciej W. Rozycki authored
Don't call the `ieee754sp_nanxcpt' and `ieee754dp_nanxcpt' sNaN quieting handlers for a qNaN supplied to floating-point format conversions or SQRT.S/SQRT.D instructions, or for a qNaN produced out of a negative operand supplied to SQRT.S/SQRT.D instructions. Return the qNaN right away in these cases. Signed-off-by:
Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9687/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Maciej W. Rozycki authored
Signed-off-by:
Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9686/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Maciej W. Rozycki authored
Commit fdffbafb [Lots of FPU bug fixes from Kjeld Borch Egevang.] replaced the two single `ieee754sp_nanxcpt' and `ieee754dp_nanxcpt' places, where sNaN quieting used to happen for single and double floating-point operations respectively, with individual qNaN instantiations across all the call sites instead. It also made most of these two functions dead code as where called on a qNaN they return right away. To revert the damage and make sNaN quieting uniform again first rewrite `ieee754sp_nanxcpt' and `ieee754dp_nanxcpt' to do the same quieting all the call sites do, that is return the default qNaN encoding for all input sNaN values; never propagate any sNaN payload bits from its trailing significand field. Signed-off-by:
Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9685/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Maciej W. Rozycki authored
Replace a hardcoded numeric bitmask for FCSR cause bits with `FPU_CSR_ALL_X' in `__build_clear_fpe'. Signed-off-by:
Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9684/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Maciej W. Rozycki authored
Changes applied to `do_cpu' over time reduced the use of the SIGILL issued with `force_sig' at the end to a single CU3 case only in the switch statement there. Move that `force_sig' call over to right where required then and toss out the pile of gotos now not needed to skip over the call, replacing them with regular breaks out of the switch. Signed-off-by:
Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9683/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Maciej W. Rozycki authored
Move CFC1/CTC1 emulation code to separate functions to avoid excessive indentation in forthcoming changes. Adjust formatting in a minor way and remove extraneous round brackets. Signed-off-by:
Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9682/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Maciej W. Rozycki authored
GCC is smart enough to substitute the final result for FLS calculations as implemented in the fallback C code we have in `__fls' and `fls' applied to constant values. The presence of inline asm defeats the compiler though, forcing it to emit extraneous CLZ/DCLZ calculation for processors that support these instructions. Use `__builtin_constant_p' then to avoid inline asm altogether for constants. Signed-off-by:
Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9681/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Maciej W. Rozycki authored
Commit 56a64733 [MIPS: math-emu: Switch to using the MIPS rounding modes.] removed the distinction between hardware and emulator rounding mode encodings, the hardware encoding is now used in emulation as well. Complement the change and remove the `modeindex' macro previously used for indexing into encoding translation tables, it now does nothing and only obfuscates code by reinserting the value extracted from FCSR. Adjust comments accordingly. Signed-off-by:
Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9680/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Maciej W. Rozycki authored
Fold a nested `if' statement for the R6 case in `do_ri' into its containing `if' block, removing excessive indentation causing code to extend beyond 79 columns. Signed-off-by:
Maciej W. Rozycki <macro@linux-mips.org> Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9679/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Maciej W. Rozycki authored
Use `static inline' rather than `static __maybe_unused' for `mipsr2_decoder' in the empty case, making inlining explicit where it will happen anyway. Signed-off-by:
Maciej W. Rozycki <macro@linux-mips.org> Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9678/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Maciej W. Rozycki authored
Commit 46490b57 [MIPS: kernel: elf: Improve the overall ABI and FPU mode checks] reduced `get_fp_abi' to an elaborate pass-through. Drop it then. Signed-off-by:
Maciej W. Rozycki <macro@linux-mips.org> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9677/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Maciej W. Rozycki authored
Signed-off-by:
Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9676/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Maciej W. Rozycki authored
Correct a copy-and-paste issue with the description for `movf_func' referring to `movt_func'. Reformat the former function to match the latter. Signed-off-by:
Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9675/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Maciej W. Rozycki authored
Correct the double-tab indentation of the branch-likely not-taken case. Signed-off-by:
Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9674/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Maciej W. Rozycki authored
Reword the comment for `__cpu_has_fpu' to make it unambiguous this code is for external floating-point units only, generally MIPS I processors using the original CP1 hardware interface. Signed-off-by:
Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9673/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Maciej W. Rozycki authored
Adjust the explanatory comment for FPU emulator traps according to ba3049ed [MIPS: Switch FPU emulator trap to BREAK instruction.]; originally coming from `do_ade'. Signed-off-by:
Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9672/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Maciej W. Rozycki authored
Add the remaining missing comments for IEEE 754 special value array indices. Reindent macro definitions for consistency. Signed-off-by:
Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9671/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Maciej W. Rozycki authored
IEEE754_SPCVAL_NMIN denotes the index into the special value array where the closest to zero negative normal number expressible is stored. Similarly IEEE754_SPCVAL_NMIND denotes such index for the closest to zero negative subnormal number expressible. Make comments match that. Signed-off-by:
Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9670/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Maciej W. Rozycki authored
Reindent CP0 Cause macros for a single space after #define, leaving extra indentation for individual Interrupt Pending bits as with CP0 Status register's Interrupt Mask bits. [ralf@linux-mips.org: Fix conflict.] [ralf@linux-mips.org: Fix indentation of the CAUSEB_FDCI and CAUSEF_FDCI definitions.] Signed-off-by:
Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9669/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Maciej W. Rozycki authored
TX39 CP0 Configuration Register 3 macro definitions have been randomly thrown in the middle of a block of CP0 Status register value macros. Move them to the end of the whole CP0 register value macro block, complementing the location of the TX39 Cache register name macro at the end of the CP0 register name macro block. [ralf@linux-mips.org: Fix conflict.] Signed-off-by:
Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9668/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Maciej W. Rozycki authored
Originally CP1 macros were placed between CP0 register name macros and CP0 register value macros. As changes were applied to the header the position of CP1 macros gradually has become more and more arbitrary and two separate blocks were created. This may only cause confusion. Move them out of the way then and place together after all the CP0 macros. No semantic change. [ralf@linux-mips.org: Fix conflict.] Signed-off-by:
Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9667/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Maciej W. Rozycki authored
Remove a duplicate FPU Status Register reference that has been there since forever and a mistakenly copied and pasted R4xx0 manual reference. [ralf@linux-mips.org: Fix conflict.] Signed-off-by:
Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9666/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Maciej W. Rozycki authored
The MIPS port has supported this option since forever, long before SH was even in plans. Signed-off-by:
Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9665/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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- 02 Apr, 2015 6 commits
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Ralf Baechle authored
Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
So let's remove everythig that only make sense for a kernel module and build the thing unconditionally. Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
So let's remove everything that only makes sense for kernel modules. Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
So let's remove everything that only makes sense for kernel modules. Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Rafał Miłecki authored
This simplifies code a lot by dropping many per-revision-group functions. There are still some paths left that use uncommon NVRAM read helpers or fill arrays. They will need to be handled in separated patch. I've tested this (by printing SPROM content) for regressions on: 1) BCM4704 (SPROM revision 2) 2) BCM4706 (SPROM revision 8 plus 11 & 9 on extra WiFi cards) The only difference is not reading board_type from SPROM rev 11 which is unsupported and treated as rev 1. This change for rev 1 is expected. Signed-off-by:
Rafał Miłecki <zajec5@gmail.com> Cc: linux-mips@linux-mips.org Cc: Hauke Mehrtens <hauke@hauke-m.de> Cc: Jonas Gorski <jonas.gorski@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/9660/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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