1. 08 Jul, 2014 10 commits
  2. 07 Jul, 2014 4 commits
  3. 03 Jul, 2014 16 commits
  4. 02 Jul, 2014 10 commits
    • Eric Dumazet's avatar
      inet: move ipv6only in sock_common · 9fe516ba
      Eric Dumazet authored
      When an UDP application switches from AF_INET to AF_INET6 sockets, we
      have a small performance degradation for IPv4 communications because of
      extra cache line misses to access ipv6only information.
      
      This can also be noticed for TCP listeners, as ipv6_only_sock() is also
      used from __inet_lookup_listener()->compute_score()
      
      This is magnified when SO_REUSEPORT is used.
      
      Move ipv6only into struct sock_common so that it is available at
      no extra cost in lookups.
      Signed-off-by: default avatarEric Dumazet <edumazet@google.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      9fe516ba
    • David S. Miller's avatar
      Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/net-next · 090cce42
      David S. Miller authored
      Jeff Kirsher says:
      
      ====================
      Intel Wired LAN Driver Updates 2014-07-01
      
      This series contains updates to i40e, i40evf, igb and ixgbe.
      
      Shannon adds the Base Address High and Low to the admin queue structure
      to simplify the logic in the configuration routines.  Also adds code to
      clear all queues and interrupts to help clean up after a PXE or other
      early boot activity.
      
      Kevin fixes mask assignment value since -1 cannot be used for unsigned
      integer types.
      
      Mitch fixes an issue where in some circumstances the reply from the PF
      would come back before we were able to properly modify the admin queue
      pending and required flags.  This would mess up the flags and put the
      driver in an indeterminate state, so fix this by simply setting the flags
      before sending the request to the admin queue.  Also changes the branding
      string for i40evf to reduce confusion and to match up with our other
      marketing materials.
      
      Kamil adds a new variable defining admin send queue (ASQ) command write
      back timeout to allow for dynamic modification of this timeout.
      
      Anjali fix a bug in the flow director filter replay logic, so that we
      call a replay after a sideband reset correctly.
      
      Jesse adds code to initialize all members of the context descriptor to
      prevent possible stale data.
      
      Christopher fixes i40e to prevent writing to reserved bits, since the
      queue index is only 0-127.
      
      Jacob removes the unneeded header export.h from the i40e PTP code.
      Fixes ixgbe PTP code where the PPS signal was not correct, as it
      generates a one half HZ clock signal, it only generates one level
      change per second.  To generate a full clock, we need two level changes
      per second.
      
      Todd provides a fix for igb to bring up link when the PHY has powered
      up, which was reported by Jeff Westfahl.
      ====================
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      090cce42
    • Jiri Pirko's avatar
      bonding: allow to add vlans on top of empty bond · 763e0ecd
      Jiri Pirko authored
      This limitation maybe had some reason in the past, but now there is not
      one -> removing this.
      Signed-off-by: default avatarJiri Pirko <jiri@resnulli.us>
      Acked-by: default avatarVeaceslav Falico <vfalico@gmail.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      763e0ecd
    • David S. Miller's avatar
      Merge branch 'cxgb4-next' · 813f8e29
      David S. Miller authored
      Hariprasad Shenai says:
      
      ====================
      cxgb4: Fix for PCI passthrough and some Misc. fixes
      
      This patch series fixes probe failure in VM when PF is exposed through PCI
      Passthrough. Adds support to use firmware interface to get BAR0 value.
      Replace the backdoor mechanism to access the HW memory with PCIe Window method
      which fixes memory I/O. Also adds device ID of few more adapters for cxgb4 and
      cxgb4vf driver.
      
      The patches series is created against 'net-next' tree.
      And includes patches on cxgb4, cxgb4vf and iw_cxgb4 driver.
      
      Since this patch-series contains mainly cxgb4 related changes, we would like to
      request this patch series to get merged via David Miller's 'net-next' tree.
      
      We have included all the maintainers of respective drivers. Kindly review the
      change and let us know in case of any review comments.
      ====================
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      813f8e29
    • Hariprasad Shenai's avatar
    • Hariprasad Shenai's avatar
    • Hariprasad Shenai's avatar
      cxgb4: Replaced the backdoor mechanism to access the HW memory with PCIe Window method · fc5ab020
      Hariprasad Shenai authored
      Rip out a bunch of redundant PCI-E Memory Window Read/Write routines,
      collapse the more general purpose routines into a single routine
      thereby eliminating the need for a large stack frame (and extra data
      copying) in the outer routine, change everything to use the improved
      routine t4_memory_rw.
      
      Based on origninal work by Casey Leedom <leedom@chelsio.com> and
      Steve Wise <swise@opengridcomputing.com>
      Signed-off-by: default avatarCasey Leedom <leedom@chelsio.com>
      Signed-off-by: default avatarSteve Wise <swise@opengridcomputing.com>
      Signed-off-by: default avatarHariprasad Shenai <hariprasad@chelsio.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      fc5ab020
    • Hariprasad Shenai's avatar
      cxgb4: Use FW interface to get BAR0 value · 0abfd152
      Hariprasad Shenai authored
      Use the firmware interface to get the BAR0 value since we really don't want
      to use the PCI-E Configuration Space Backdoor access which is owned by the
      firmware.
      
      Set up PCI-E Memory Window registers using the true values programmed into
      BAR registers.  When the PF4 "Master Function" is exported to a Virtual
      Machine, the values returned by pci_resource_start() will be for the
      synthetic PCI-E Configuration Space and not the real addresses. But we need
      to program the PCI-E Memory Window address decoders with the real addresses
      that we're going to be using in order to have accesses through the Memory
      Windows work.
      
      Based on origninal work by Casey Leedom <leedom@chelsio.com>
      Signed-off-by: default avatarCasey Leedom <leedom@chelsio.com>
      Signed-off-by: default avatarHariprasad Shenai <hariprasad@chelsio.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      0abfd152
    • Hariprasad Shenai's avatar
      rdma/cxgb4: Fixes cxgb4 probe failure in VM when PF is exposed through PCI Passthrough · 35b1de55
      Hariprasad Shenai authored
      Change logic which determines our Physical Function at PCI Probe time.
      Now we read the PL_WHOAMI register and get the Physical Function.
      
      Pass Physical Function to Upper Layer Drivers in lld_info structure in the
      new field "pf" added to lld_info.  This is useful for the cases where the
      PF, say PF4, is attached to a Virtual Machine via some form of "PCI
      Pass Through" technology and the PCI Function shows up as PF0 in the VM.
      
      Based on original work by Casey Leedom <leedom@chelsio.com>
      Signed-off-by: default avatarCasey Leedom <leedom@chelsio.com>
      Signed-off-by: default avatarHariprasad Shenai <hariprasad@chelsio.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      35b1de55
    • David S. Miller's avatar
      Merge branch 'dp83640-next' · 2eb27a16
      David S. Miller authored
      Stefan Sørensen says:
      
      ====================
      dp83640: Increase support perout pins
      
      This patch series increases the number of periodic output pins supported
      on the dp83640 to 7, and allows for reprogramming the calibration pin.
      ====================
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      2eb27a16