- 03 Sep, 2024 39 commits
-
-
Christophe Leroy authored
Herve Codina says: ================ This series add support for the QUICC Engine (QE) version of TSA and QMC components. CPM1 version is already supported and, as the QE version of those component are pretty similar to the CPM1 version, the series extend the already existing drivers to support for the QE version. The TSA and QMC components are tightly coupled and so the series provides modifications on both components. Of course, this series can be split if it is needed. Let me know. The series is composed of: - Patches 1 and 2: Fixes related to TRNSYNC in the QMC driver - Patches 3..6: Fixes of checkpatch detected issues in the TSA driver - Patch 7: The QE TSA device-tree binding - Patches 8..13: TSA driver preparations for adding support for QE - Patches 14 and 15: The support for QE in TSA + MAINTAINERS update - Patch 16: A TSA API improvement needed for the QE QMC driver - Patch 17: A clarification in the QE QMC driver - Patches 18..22: Fixes of checkpatch detected issues in the QMC driver - Patch 23: The QE QMC device-tree binding - Patches 24..31: QMC driver preparations for adding support for QE - Patches 32 and 33: Missing features additions in QE code - Patches 34..36: The QMC support for QE in QMC + MAINTAINERS update Compared to the previous iteration, this v2 series updates device-tree bindings and fixes issues detected by kernel test robots. Related to the QE QMC device-tree binding, I kept the unit address in decimal and the 3 compatible strings. ================ Link: https://lore.kernel.org/r/20240808071132.149251-1-herve.codina@bootlin.comSigned-off-by:
Christophe Leroy <christophe.leroy@csgroup.eu> Tested-by:
-
Xiaolei Wang authored
This warning was added by commit 07f86917 ("soc/fsl/qbman: Use shared-dma-pool for QMan private memory allocations") but RESERVEDMEM_OF_DECLARE usage was removed by commit 3e62273a ("soc: fsl: qbman: Remove RESERVEDMEM_OF_DECLARE usage") . For non-popwerpc platforms, such as ls1043, this warning is redundant. ls1043 itself uses shared-dma-mem. Fixes: 3e62273a ("soc: fsl: qbman: Remove RESERVEDMEM_OF_DECLARE usage") Signed-off-by:
Xiaolei Wang <xiaolei.wang@windriver.com> Link: https://lore.kernel.org/r/20240802021651.3854295-1-xiaolei.wang@windriver.com [chleroy: Added more details in commit message] Signed-off-by:
-
Lu Baolu authored
An iommu domain is allocated in portal_set_cpu() and is attached to pcfg->dev in the same function. Use iommu_paging_domain_alloc() to make it explicit. Signed-off-by:
Lu Baolu <baolu.lu@linux.intel.com> Reviewed-by:
Jason Gunthorpe <jgg@nvidia.com> Link: https://lore.kernel.org/r/20240610085555.88197-14-baolu.lu@linux.intel.comSigned-off-by:
-
Herve Codina authored
The Freescale QMC controller driver supports both QE and CPM1. Add the newly introduced QE files to the existing entry. Signed-off-by:
Herve Codina <herve.codina@bootlin.com> Reviewed-by:
-
Herve Codina authored
The QUICC Engine (QE) QMC can use a firmware to have the QMC working in 'soft-qmc' mode. Handle this optional 'soft-qmc' firmware. Signed-off-by:
-
Herve Codina authored
Add support for the QMC (QUICC Multichannel Controller) available in some PowerQUICC SoC that uses a QUICC Engine (QE) block such as MPC8321. This QE QMC is similar to the CPM QMC except that it uses UCCs (Unified Communication Controllers) instead of SCCs (Serial Communication Controllers). Also, compared against the CPM QMC, this QE QMC does not use a fixed area for the UCC/SCC parameters area but it uses a dynamic area allocated and provided to the hardware at runtime. Signed-off-by:
-
Herve Codina authored
The PUSHSCHED command is missing in the QE header file. This command is supported on MPC8321 and is used to modify the start address for the task running on a given peripheral. It is needed for the QMC in order to perform the re-initialization procedure and so, ensure the correct UCC setup in that case. Simply add the missing command in the commands list available in the QE header file. Signed-off-by:
-
Herve Codina authored
Introduce devm_cpm_muram_alloc() and devm_cpm_muram_alloc_fixed(), the resource-managed version of cpm_muram_alloc and cpm_muram_alloc_fixed(). These resource-managed versions simplify the user avoiding the need to call cpm_muram_free(). Indeed, the allocated area returned by these functions will be automatically freed on driver detach. Signed-off-by:
-
Herve Codina authored
Current code handles the CPM1 version of QMC. In order to prepare the support for the QUICC Engine (QE) version of QMC, introduce qmc_version to identify versions. This will enable the code to make the distinction between several QMC implementations. Signed-off-by:
-
Herve Codina authored
Current code handles CPM1 version of QMC. Even if GSMRL is specific to the CPM1 version, the exact same purpose and format register (GUMRL) is present in the QUICC Engine (QE) version of QMC. Compared to the QE version, the values defined for the mode bitfield are different and the 0x0A value defined for the QMC mode is CPM1 specific. In order to prepare the support for the QE version, rename this bitfield value to clearly identify it as CPM1 specific. Signed-off-by:
-
Herve Codina authored
Current code handles the CPM1 version of QMC, RPACK does not need to be initialized. This is not the case in the QUICC Engine (QE) version. In preparation of the support for QE, initialize the RPACK register when the receiver is initialized and each time it is restarted. This additional RPACK initialization has no impact in the CPM1 version of QMC. Signed-off-by:
-
Herve Codina authored
Current code handles CPM1 version of QMC and qmc_chan_command() is clearly CPM1 specific. In order to prepare the support for the QUICC Engine (QE) version, rename qmc_chan_command() to reflect that point. Signed-off-by:
-
Herve Codina authored
Current code handles the CPM1 version of QMC and initialize the QMC used SCC. The QUICC Engine (QE) version uses an UCC (Unified Communication Controllers) instead of the SCC (Serial Communication Controllers) used in the CPM1 version. These controllers serve the same purpose and are used in the same way but their inializations are slightly different. In order to prepare the support for QE version of QMC, introduce qmc_init_xcc() to initialize theses controllers (UCC in QE and SCC in CPM1) and isolate the CPM1 specific SCC initialization in a specific function. Also introduce qmc_exit_xcc() for consistency to revert operations done in qmc_init_xcc(). Signed-off-by:
-
Herve Codina authored
Current code handles the CPM1 version of QMC. Resources initialisations (i.e. retrieving base addresses and offsets of different parts) will be slightly different in the QUICC Engine (QE) version. Indeed, in QE version, some resources need to be allocated and are no more "staticaly" defined. In order to prepare the support for QE version, introduce qmc_init_resource() to initialize those resources and isolate the CPM1 specific operations in a specific function. Signed-off-by:
-
Herve Codina authored
Current code handles CPM1 version of QMC. In the QUICC Engine (QE) version, some operations done at probe() need to be done in a different order. In order to prepare the support for the QE version, changed the sequence of operation done at probe(): - Retrieve the tsa_serial earlier, before initializing resources. - Group SCC initialisation and do this initialization when it is really needed in the probe() sequence. Having the QE compatible sequence in the CPM1 version does not lead to any issue and works correctly without any regressions. Signed-off-by:
-
Herve Codina authored
Current code handles CPM1 version of QMC. Some hardcoded values are used several times to initialize the QMC state machine. In the QUICC Engine (QE) version of QMC, these values are different. In order to prepare the support for the QE version of QMC and avoid the copy of the hardcoded values, introduce the qmc_data structure to define these version specific values. Signed-off-by:
-
Herve Codina authored
Add support for the QMC (QUICC Multichannel Controller) available in some PowerQUICC SoC that uses a QUICC Engine (QE) block such as MPC8321. This QE QMC is similar to the CPM QMC except that it uses UCCs (Unified Communication Controllers) instead of SCCs (Serial Communication Controllers). Also, compared against the CPM QMC, this QE QMC does not use a fixed area for the UCC/SCC parameters area but it uses a dynamic area allocated and provided to the hardware at runtime. Last point, the QE QMC can use a firmware to have the QMC working in 'soft-qmc' mode. Signed-off-by:
-
Herve Codina authored
checkpatch.pl raises the following issue CHECK: spinlock_t definition without comment Add the missing comments. Signed-off-by:
-
Herve Codina authored
checkpatch.pl raises the following issue CHECK: 'transmiter' may be misspelled - perhaps 'transmitter'? Indeed, fix it. Signed-off-by:
-
Herve Codina authored
checkpatch.pl raises the following issue in several places CHECK: Unnecessary parenthesis around ... Remove them. Signed-off-by:
-
Herve Codina authored
checkpatch.pl raises the following issues CHECK: Please don't use multiple blank lines CHECK: Alignment should match open parenthesis Fix them. Signed-off-by:
-
Herve Codina authored
checkpatch.pl signals the following improvement for qmc.c CHECK: Prefer using the BIT macro Follow its suggestion and convert the code to BIT() and related macros. Signed-off-by:
-
Herve Codina authored
QMC_TSA_MASK is a bitfield. The value defined is a specific value of this bitfield and correspond to the use of 8bit resolution for the routing entry. Be accurate and rename the defined constant to reflect this point. Signed-off-by:
-
Herve Codina authored
TSA consumers in CPM1 implementation don't need to know about the serial device number used by the TSA component. In QUICC Engine implementation, this information is needed. Improve the TSA API with tsa_serial_get_num() in order to provide this information. Signed-off-by:
-
Herve Codina authored
The Freescale TSA controller driver supports both QE and CPM1. Add the newly introduced QE files to the existing entry. Signed-off-by:
-
Herve Codina authored
Add support for the time slot assigner (TSA) available in some PowerQUICC SoC that uses a QUICC Engine (QE) block such as MPC8321. The QE TSA is similar to the CPM1 TSA except that it uses UCCs (Unified Communication Controllers) instead of SCCs (Serial Communication Controllers). Also, compared against the CPM1 TSA, this QE TSA can handle up to 4 TDMs instead of 2 and allows to configure the logic level of sync signals. At a lower level, compared against CPM TSA implementation, some registers are slightly different even if same features are present. Signed-off-by:
-
Herve Codina authored
Current code handles CPM1 version of TSA. In order to prepare the support for the QUICC Engine (QE) version of TSA, introduce tsa_version to identify versions. This will enable the code to make the distinction between several TSA implementations. Signed-off-by:
-
Herve Codina authored
Current code handles the CPM1 version of TSA. Connecting and disconnecting the SCC to/from the TSA consists in handling SICR register which is CPM1 specific. The connection and disconnection operation in the QUICC Engine (QE) version are slightly different. In order to prepare the support for the QE version, clearly identify SICR register as specific to CPM1 and isolate its handling done in connect and disconnect functions. Signed-off-by:
-
Herve Codina authored
Current code handles the CPM1 version of TSA. Setting up TSA consists in handling SIMODE and SIGMR registers. These registers are CPM1 specific. Setting up the QUICC Engine (QE) version of TSA is slightly different. In order to prepare the support for QE version, clearly identify these registers as CPM1 compatible and isolate their handling in a CPM1 specific function. Signed-off-by:
-
Herve Codina authored
Current code handles the CPM1 version of TSA. Compared against QUICC Engine (QE) version of TSA, CPM1 SIRAM entries are slightly different. In order to prepare the support for the QE version, clearly identify these entries and functions handling them as CPM1 compatible. Signed-off-by:
-
Herve Codina authored
Loops handling the tdm array use hardcoded size and the initialization part uses hardcoded indexes to initialize the array. Use ARRAY_SIZE() to avoid the hardcoded size and initialize the array using a loop. Signed-off-by:
-
Herve Codina authored
SISTR, SICMR and SIRP registers offset definitions are not used. In order to avoid unneeded code, remove them. Signed-off-by:
-
Herve Codina authored
Add support for the time slot assigner (TSA) available in some PowerQUICC SoC that uses a QUICC Engine (QE) block such as MPC8321. This QE TSA is similar to the CPM TSA except that it uses UCCs (Unified Communication Controllers) instead of SCCs (Serial Communication Controllers). Also, compared against the CPM TSA, this QE TSA can handle up to 4 TDMs instead of 2 and allows to configure the logic level of sync signals. Signed-off-by:
Rob Herring (Arm) <robh@kernel.org> Reviewed-by:
-
Herve Codina authored
checkpatch.pl raises the following issue CHECK: spinlock_t definition without comment Add the missing comment. Signed-off-by:
-
Herve Codina authored
checkpatch.pl raises the following issues CHECK: Please don't use multiple blank lines CHECK: spaces preferred around that '/' (ctx:VxV) CHECK: spaces preferred around that '+' (ctx:VxV) CHECK: spaces preferred around that '-' (ctx:VxV) Fix them. Signed-off-by:
-
Herve Codina authored
checkpatch.pl signals the following improvement for tsa.c CHECK: Prefer using the BIT macro Follow its suggestion and convert the code to BIT() and related macros. Signed-off-by:
-
Herve Codina authored
The tsa_write8() parameter is an u32 value. This is not consistent with the function itself. Indeed, tsa_write8() writes an 8bits value. Be consistent and use an u8 parameter value. Fixes: 1d4ba0b8 ("soc: fsl: cpm1: Add support for TSA") Cc: stable@vger.kernel.org Signed-off-by:
-
Herve Codina authored
The TRNSYNC feature is enabled whatever the number of time-slots used. The feature is needed only when more than one time-slot is used. Improve the driver enabling TRNSYNC only when it is needed. Signed-off-by:
-
Herve Codina authored
The TRNSYNC feature is available (and enabled) only in transparent mode. Since commit 7cc9bda9 ("soc: fsl: cpm1: qmc: Handle timeslot entries at channel start() and stop()") TRNSYNC register is updated in transparent and hdlc mode. In hdlc mode, the address of the TRNSYNC register is used by the QMC for other internal purpose. Even if no weird results were observed in hdlc mode, touching this register in this mode is wrong. Update TRNSYNC only in transparent mode. Fixes: 7cc9bda9 ("soc: fsl: cpm1: qmc: Handle timeslot entries at channel start() and stop()") Cc: stable@vger.kernel.org Signed-off-by:
-
- 28 Jul, 2024 1 commit
-
-
Linus Torvalds authored
-
