- 22 Feb, 2021 1 commit
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Nathan Chancellor authored
Clang warns: drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu_cmn.c:764:2: warning: variable 'structure_size' is used uninitialized whenever switch default is taken [-Wsometimes-uninitialized] default: ^~~~~~~ drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu_cmn.c:770:23: note: uninitialized use occurs here memset(header, 0xFF, structure_size); ^~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu_cmn.c:753:25: note: initialize the variable 'structure_size' to silence this warning uint16_t structure_size; ^ = 0 1 warning generated. Return in the default case, as the size of the header will not be known. Fixes: de4b7cd8 ("drm/amd/pm/swsmu: unify the init soft gpu metrics function") Link: https://github.com/ClangBuiltLinux/linux/issues/1304Reviewed-by:Kevin Wang <kevin1.wang@amd.com> Signed-off-by:
Nathan Chancellor <nathan@kernel.org> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- 19 Feb, 2021 2 commits
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Dave Airlie authored
Merge tag 'drm-intel-next-fixes-2021-02-18' of git://anongit.freedesktop.org/drm/drm-intel into drm-next - Restrict DRM_I915_DEBUG to developer builds (Chris) - Fix return and error codes (Dan) - Suspend/Resume fix (Chris) - Disable atomics in L3 for gen9 (Chris) - Flush before changing register state (Chris) - Fix for GLK's HDMI (Ville) - Fix ILK+'s plane strides with Xtiling (Ville) - Correct surface base address for renderclear (Chris) Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/YC7uQY1kt6w0tRp+@intel.com
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Dave Airlie authored
Merge tag 'amd-drm-next-5.12-2021-02-18' of https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-5.12-2021-02-18: amdgpu: - Prefer Bhawan's unused variable fix - Fixes for high priority queues on gfx8,9 - swSMU fixes for sienna cichlid - swSMU fixes for renoir - mmhub client id fixes for arcturus - SMUIO fixes for navi family - swSMU fixes for vangogh - GPU reset cleanup - Display fixes - GFX harvesting fix for sienna cichlid - Fix reference clock on Renoir - Misc fixes and cleanups amdkfd: - Fix for unique id query - Fix recursive lock warnings radeon: - Remove confusing VCE messages on Oland Signed-off-by:
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- 18 Feb, 2021 7 commits
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Alex Deucher authored
Fixes the rlc reference clock used for GPU timestamps. Value is 100Mhz. Confirmed with hardware team. v2: reword commit message. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1480Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Alex Deucher authored
Disable it on those boards. No functional change, this just removes the message about VCE failing to initialize. Bug: https://bugzilla.kernel.org/show_bug.cgi?id=197327Reviewed-by:
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Felix Kuehling authored
memalloc_nofs_save/restore are no longer sufficient to prevent recursive lock warnings when holding locks that can be taken in MMU notifiers. Use memalloc_noreclaim_save/restore instead. Fixes: f920e413 ("mm: track mmu notifiers in fs_reclaim_acquire/release") CC: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by:
Philip Yang <Philip.Yang@amd.com> Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Jan Kokemüller authored
dcn21_validate_bandwidth() calls functions that use floating point math. On my machine this sometimes results in simd exceptions when there are other FPU users such as KVM virtual machines running. The screen freezes completely in this case. Wrapping the function with DC_FP_START()/DC_FP_END() seems to solve the problem. This mirrors the approach used for dcn20_validate_bandwidth. Tested on a AMD Ryzen 7 PRO 4750U (Renoir). Bug: https://bugzilla.kernel.org/show_bug.cgi?id=206987Signed-off-by:
Jan Kokemüller <jan.kokemueller@gmail.com> Signed-off-by:
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Gustavo A. R. Silva authored
Fix potential integer overflow by casting actual_calculated_clock_100hz to u64, in order to give the compiler complete information about the proper arithmetic to use. Notice that such variable is used in a context that expects an expression of type u64 (64 bits, unsigned) and the following expression is currently being evaluated using 32-bit arithmetic: actual_calculated_clock_100hz * post_divider Fixes: 7a03fdf6 ("drm/amd/display: fix 64bit division issue on 32bit OS") Addresses-Coverity-ID: 1501691 ("Unintentional integer overflow") Signed-off-by:
Gustavo A. R. Silva <gustavoars@kernel.org> Signed-off-by:
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Nirmoy Das authored
Fixes: 9037246b ("drm/amd/display: Add sysfs interface for set/get srm") Signed-off-by:
Nirmoy Das <nirmoy.das@amd.com> Acked-by:
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Marek Olšák authored
This fixes incorrect TCC harvesting info reported to userspace. The impact was a very very tiny performance degradation (unnecessary GL2 cache flushes). Signed-off-by:
Marek Olšák <marek.olsak@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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- 17 Feb, 2021 2 commits
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Chris Wilson authored
The surface_state_base is an offset into the batch, so we need to pass the correct batch address for STATE_BASE_ADDRESS. Fixes: 47f8253d ("drm/i915/gen7: Clear all EU/L3 residual contexts") Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com> Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com> Cc: Hans de Goede <hdegoede@redhat.com> Reviewed-by:
Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: <stable@vger.kernel.org> # v5.7+ Link: https://patchwork.freedesktop.org/patch/msgid/20210210122728.20097-1-chris@chris-wilson.co.uk (cherry picked from commit 1914911f4aa08ddc05bae71d3516419463e0c567) Signed-off-by:
Rodrigo Vivi <rodrigo.vivi@intel.com>
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Ville Syrjälä authored
ilk+ planes get notably unhappy when the plane x+w exceeds the stride. This wasn't a problem previously because we always aligned SURF to the closest tile boundary so the x offset never got particularly large. But now with async flips we have to align to 256KiB instead and thus this becomes a real issue. On ilk/snb/ivb it looks like the accesses just wrap early to the next tile row when scanout goes past the SURF+n*stride boundary, hsw/bdw suffer more heavily and start to underrun constantly. i965/g4x appear to be immune. vlv/chv I've not yet checked. Let's borrow another trick from the skl+ code and search backwards for a better SURF offset in the hopes of getting the x offset below the limit. IIRC when I ran into a similar issue on skl years ago it was causing the hardware to fall over pretty hard as well. And let's be consistent and include i965/g4x in the check as well, just in case I just got super lucky somehow when I wasn't able to reproduce the issue. Not that it really matters since we still use 4k SURF alignment for i965/g4x anyway. Fixes: 6ede6b06 ("drm/i915: Implement async flips for vlv/chv") Fixes: 4bb18054 ("drm/i915: Implement async flip for ilk/snb") Fixes: 2a636e24 ("drm/i915: Implement async flip for ivb/hsw") Fixes: cda195f1 ("drm/i915: Implement async flips for bdw") Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210209021918.16234-1-ville.syrjala@linux.intel.comReviewed-by:
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- 12 Feb, 2021 2 commits
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Dave Airlie authored
Merge tag 'drm-misc-next-fixes-2021-02-11' of git://anongit.freedesktop.org/drm/drm-misc into drm-next drm-misc-next-fixes cherry picked from drm-misc-next for v5.12: - Assorted small fixes. - Disable and remove gma3600 support. - Fix CEC for vc4/hdmi. Signed-off-by:
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git://github.com/skeggsb/linuxDave Airlie authored
Ben wrote: The problem is that GA100 added enough new engine types and instances that we would have begun to overflow various u64 bitfields used to track the connections between various engines. Rather than addressing subdevs by a unique index, we give each subdev a type and instance id, and replace the use of bitfields tied to subdev index with other methods. Notable changes: - replace subdev index with subdev type + instance id - engines that turn out to be fused-off (can't detect until later in init) no longer leave dangling pointers around - new subdev/instance additions no longer need to be made in multiple places - ampere engine topology is now being parsed Signed-off-by:
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- 11 Feb, 2021 26 commits
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Ben Skeggs authored
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Ben Skeggs <bskeggs@redhat.com> Reviewed-by:
Lyude Paul <lyude@redhat.com>
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
Instead of subdev index. Signed-off-by:
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Ben Skeggs authored
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Ben Skeggs authored
This data is used to know which engines/classes are reachable on a given channel's runlist, and needs to be replaced with something that doesn't rely on subdev index. Signed-off-by:
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