- Fix typos and whitespace errors (Bjorn Helgaas)

* pci/trivial:
  PCI: Fix typos and whitespace errors

  - Fix pcitest build issues (Alan Mikhak)

  - Fix pcitest installation issue (Andy Shevchenko)

* remotes/lorenzo/pci/misc:
  tools: PCI: Fix installation when `make tools/pci_install`
  tools: PCI: Fix compiler warning in pcitest
  tools: PCI: Fix broken pcitest compilation

  - Complete PCI endpoint removal so a subsequent add doesn't fail with
    -EBUSY (Alan Mikhak)

  - Pay attention to PCI endpoint fixed-size BARs (Alan Mikhak)

  - Fix PCI endpoint handling of 64bit BARs (Alan Mikhak)

  - Clear PCI endpoint BARs before freeing space (Alan Mikhak)

* remotes/lorenzo/pci/endpoint:
  PCI: endpoint: Clear BAR before freeing its space
  PCI: endpoint: Skip odd BAR when skipping 64bit BAR
  PCI: endpoint: Allocate enough space for fixed size BAR
  PCI: endpoint: Set endpoint controller pointer to NULL

  - Fix Xilinx NWL multi-MSI vector aliasing issue (Bharat Kumar Gogada)

* remotes/lorenzo/pci/xilinx:
  PCI: xilinx-nwl: Fix Multi MSI data programming

  - Reorganize Tegra AFI/PHY/REFCLK/etc functions (Manikanta Maddireddy)

  - Mask Tegra AFI_INTR in runtime suspend (Manikanta Maddireddy)

  - Fix Tegra AFI/PCIe powerup sequence (Manikanta Maddireddy)

  - Add Tegra124, Tegra132, Tegra210, and Tegra186 support for Gen2 link
    speed (Manikanta Maddireddy)

  - Advertise Tegra AER support (Manikanta Maddireddy)

  - Program Tegra210 UPHY settings (Manikanta Maddireddy)

  - Enable Tegra opportunistic UpdateFC and ACK (Manikanta Maddireddy)

  - Disable Tegra AFI dynamic clock gating (Manikanta Maddireddy)

  - Process Tegra pending DLL transactions before entering L1 or L2 to
    prevent receiver errors (Manikanta Maddireddy)

  - Enable Tegra xclk clock clamping in L1 (Manikanta Maddireddy)

  - Increase Tegra deskew retry time (Manikanta Maddireddy)

  - Work around Tegra hardware RAW erratum (Manikanta Maddireddy)

  - Update Tegra210 flow control timer frequency (Manikanta Maddireddy)

  - Work around Tegra Gen1/Gen2 link number negotiation issue (Manikanta
    Maddireddy)

  - Work around Tegra PLLE power down issue (Manikanta Maddireddy)

  - Program Tegra20 to support cacheable upstream transactions (Manikanta
    Maddireddy)

  - Log Tegra PRSNT_SENSE_IRQ as debug, not err (Manikanta Maddireddy)

  - Add register offset for third Root Port on Tegra186 and Tegra30
    (Manikanta Maddireddy)

  - Document Tegra PCIe DPD pinctrl property (Manikanta Maddireddy)

  - Put Tegra PEX CLK & BIAS pads in DPD mode to reduce power usage when
    powergated (Manikanta Maddireddy)

  - Add generic DT binding for "reset-gpios" property (Manikanta
    Maddireddy)

  - Add Tegra support for GPIO-based PERST# (Manikanta Maddireddy)

  - Enable Relaxed Ordering only for Tegra20 & Tegra30 (Vidya Sagar)

* remotes/lorenzo/pci/tegra:
  PCI: tegra: Enable Relaxed Ordering only for Tegra20 & Tegra30
  PCI: tegra: Change link retry log level to debug
  PCI: tegra: Add support for GPIO based PERST#
  PCI: Add DT binding for "reset-gpios" property
  PCI: tegra: Put PEX CLK & BIAS pads in DPD mode
  dt-bindings: pci: tegra: Document PCIe DPD pinctrl optional prop
  PCI: tegra: Add AFI_PEX2_CTRL reg offset as part of SoC struct
  PCI: tegra: Change PRSNT_SENSE IRQ log to debug
  PCI: tegra: Program AFI_CACHE_BAR_{0,1}_{ST,SZ} registers only for Tegra20
  PCI: tegra: Fix PLLE power down issue due to CLKREQ# signal
  PCI: tegra: Set target speed as Gen1 before starting LTSSM
  PCI: tegra: Update flow control timer frequency in Tegra210
  PCI: tegra: Add SW fixup for RAW violations
  PCI: tegra: Increase the deskew retry time
  PCI: tegra: Enable PCIe xclk clock clamping
  PCI: tegra: Process pending DLL transactions before entering L1 or L2
  PCI: tegra: Disable AFI dynamic clock gating
  PCI: tegra: Enable opportunistic UpdateFC and ACK
  PCI: tegra: Program UPHY electrical settings for Tegra210
  PCI: tegra: Advertise PCIe Advanced Error Reporting (AER) capability
  PCI: tegra: Add PCIe Gen2 link speed support
  PCI: tegra: Fix PCIe host power up sequence
  PCI: tegra: Mask AFI_INTR in runtime suspend
  PCI: tegra: Rearrange Tegra PCIe driver functions
  PCI: tegra: Handle failure cases in tegra_pcie_power_on()
  soc/tegra: pmc: Export tegra_powergate_power_on()

  - Add R-Car device tree support for r8a774a1 (Biju Das)

* remotes/lorenzo/pci/rcar:
  dt-bindings: PCI: rcar: Add device tree support for r8a774a1

  - Move qcom driver to bulk clock API (Bjorn Andersson)

  - Add Qualcomm QCS404 PCIe controller support (Bjorn Andersson)

  - Ensure Qualcomm PERST is asserted for at least 100ms (Niklas Cassel)

* remotes/lorenzo/pci/qcom:
  PCI: qcom: Ensure that PERST is asserted for at least 100 ms
  PCI: qcom: Add QCS404 PCIe controller support
  dt-bindings: PCI: qcom: Add QCS404 to the binding
  PCI: qcom: Use clk bulk API for 2.4.0 controllers

  - Unify mobiveil register accessors (Hou Zhiqiang)

  - Remove MSI_FLAG_MULTI_PCI_MSI since mobiveil hardware doesn't support
    Multiple MSI (Hou Zhiqiang)

  - Program outbound windows with base address from DT instead of assuming
    zero (Hou Zhiqiang)

  - Skip "safe" list traversal when it's unnecessary (Hou Zhiqiang)

  - Initialize WIN_NUM_0 explicitly for CFG outbound transactions (Hou
    Zhiqiang)

  - Use WIN_NUM_0 for MEM inbound transactions (Hou Zhiqiang)

  - Fix up mobiveil Class Code to PCI_CLASS_BRIDGE_PCI (Hou Zhiqiang)

  - Wait for link-up before enumerating devices, not while initializing
    host (Hou Zhiqiang)

  - Move IRQ chained handler setup out of DT code (Hou Zhiqiang)

  - Set primary/secondary/subordinate bus numbers (Hou Zhiqiang)

  - Fix "valid device" check to allow root bus device 0 to be
    multi-function (Hou Zhiqiang)

  - Make DT "gpio_slave" and "apb_csr" properties optional (Hou Zhiqiang)

  - Refactor MEM/IO outbound window initialization (Hou Zhiqiang)

  - Fix validity check for inbound/outbound window programming (Hou
    Zhiqiang)

  - Initialize and preserve window control bits (Hou Zhiqiang)

  - Fix 64-bit outbound window setup (both CPU and PCI addresses) (Hou
    Zhiqiang)

  - Move IO port setup to host init (Hou Zhiqiang)

  - Fix infinite loop in INTx ISR (Hou Zhiqiang)

  - Fix INTx interrupt clearing to avoid missed interrupts (Hou Zhiqiang)

* remotes/lorenzo/pci/mobiveil:
  PCI: mobiveil: Fix INTx interrupt clearing in mobiveil_pcie_isr()
  PCI: mobiveil: Fix infinite-loop in the INTx handling function
  PCI: mobiveil: Move PCIe PIO enablement out of inbound window routine
  PCI: mobiveil: Add upper 32-bit PCI base address setup in inbound window
  PCI: mobiveil: Add upper 32-bit CPU base address setup in outbound window
  PCI: mobiveil: Mask out hardcoded bits in inbound/outbound windows setup
  PCI: mobiveil: Clear the control fields before updating it
  PCI: mobiveil: Add configured inbound windows counter
  PCI: mobiveil: Fix the valid check for inbound and outbound windows
  PCI: mobiveil: Clean-up program_{ib/ob}_windows()
  PCI: mobiveil: Remove an unnecessary return value check
  PCI: mobiveil: Fix error return values
  PCI: mobiveil: Refactor the MEM/IO outbound window initialization
  PCI: mobiveil: Make some register updates more readable
  PCI: mobiveil: Reformat the code for readability
  dt-bindings: PCI: mobiveil: Change gpio_slave and apb_csr to optional
  PCI: mobiveil: Fix devfn check in mobiveil_pcie_valid_device()
  PCI: mobiveil: Initialize Primary/Secondary/Subordinate bus numbers
  PCI: mobiveil: Move IRQ chained handler setup out of DT parse
  PCI: mobiveil: Move the link up waiting out of mobiveil_host_init()
  PCI: mobiveil: Fix the Class Code field
  PCI: mobiveil: Use the 1st inbound window for MEM inbound transactions
  PCI: mobiveil: Use WIN_NUM_0 explicitly for CFG outbound window
  PCI: mobiveil: Update the resource list traversal function
  PCI: mobiveil: Fix PCI base address in MEM/IO outbound windows
  PCI: mobiveil: Remove the flag MSI_FLAG_MULTI_PCI_MSI
  PCI: mobiveil: Unify register accessors

  - Fix Hyper-V use-after-free in eject path (Dexuan Cui)

* remotes/lorenzo/pci/hv:
  PCI: hv: Fix a use-after-free bug in hv_eject_device_work()

  - Add dwc API support to de-initialize host (Vidya Sagar)

  - Clean up dwc DBI,ATU read and write APIs (Vidya Sagar)

  - Export dwc APIs to support .remove() so drivers can be modular (Vidya
    Sagar)

  - Simplify imx6 Kconfig dependencies (Leonard Crestez)

  - Fix dra7xx build error when !CONFIG_GPIOLIB (YueHaibing)

* remotes/lorenzo/pci/dwc:
  PCI: dwc: pci-dra7xx: Fix compilation when !CONFIG_GPIOLIB
  PCI: imx6: Simplify Kconfig depends on
  PCI: dwc: Export APIs to support .remove() implementation
  PCI: dwc: Cleanup DBI,ATU read and write APIs
  PCI: dwc: Add API support to de-initialize host

  - Add Armada8k PHYs support (Miquel Raynal)

* remotes/lorenzo/pci/armada:
  PCI: armada8k: Add PHYs support

  - Allow building Altera host bridge driver as a module (Ley Foon Tan)

  - Fix Altera Stratix 10 Type 1 to Type 0 config access conversion (Ley
    Foon Tan)

* remotes/lorenzo/pci/altera:
  PCI: altera: Fix configuration type based on secondary number
  PCI: altera-msi: Allow building as module
  PCI: altera: Allow building as module

  - Fix problem with caching VF config space size (Alex Williamson)

* pci/virtualization:
  PCI/IOV: Assume SR-IOV VFs support extended config space.
  Revert "PCI/IOV: Use VF0 cached config space size for other VFs"

  - Evaluate ACPI "PCI Boot Configuration"_DSM (Benjamin Herrenschmidt)

  - Don't auto-realloc if we're preserving firmware config (Benjamin
    Herrenschmidt)

  - Allow arm64 to reallocate resources if necessary (Benjamin
    Herrenschmidt)

  - Preserve firmware config on arm64 when desired (Benjamin Herrenschmidt)

  - Simplify resource distribution to hotplug bridges (Nicholas Johnson)

* pci/resource:
  PCI: Skip resource distribution when no hotplug bridges
  PCI: Simplify pci_bus_distribute_available_resources()
  arm64: PCI: Preserve firmware configuration when desired
  arm64: PCI: Allow resource reallocation if necessary
  PCI: Don't auto-realloc if we're preserving firmware config
  PCI/ACPI: Evaluate PCI Boot Configuration _DSM

  - Prevent drivers that use dma_virt_ops from using peer-to-peer DMA
    (Logan Gunthorpe)

* pci/peer-to-peer:
  PCI/P2PDMA: Fix missing check for dma_virt_ops

  - Generalize multi-function power dependency device links (Abhishek Sahu)

  - Add NVIDIA GPU multi-function power dependencies (Abhishek Sahu)

  - Optimize /proc/bus/pci/devices by using seq_puts() instead of
    seq_printf() (Markus Elfring)

  - Enable NVIDIA HDA controllers if BIOS didn't (Lukas Wunner)

* pci/misc:
  PCI: Enable NVIDIA HDA controllers
  PCI: Use seq_puts() instead of seq_printf() in show_device()
  PCI: Add NVIDIA GPU multi-function power dependencies
  PCI: Generalize multi-function power dependency device links

  - If user prevents VF probing, return error instead of pretending a
    driver has claimed the VF (Alex Williamson)

  - Always allow probing with driver_override (Alex Williamson)

  - Decode PCIe 32 GT/s link speed (Gustavo Pimentel)

  - Ignore lockdep for sysfs remove to avoid lockdep false positive (Marek
    Vasut)

* pci/enumeration:
  PCI: sysfs: Ignore lockdep for remove attribute
  PCI: Decode PCIe 32 GT/s link speed
  PCI: Always allow probing with driver_override
  PCI: Return error if cannot probe VF

  - Convert docs to reST (Changbin Du)

  - Convert PM docs to reST (Mauro Carvalho Chehab)

* pci/docs:
  docs: power: convert docs to ReST and rename to *.rst
  Documentation: PCI: convert endpoint/pci-test-howto.txt to reST
  Documentation: PCI: convert endpoint/pci-test-function.txt to reST
  Documentation: PCI: convert endpoint/pci-endpoint-cfs.txt to reST
  Documentation: PCI: convert endpoint/pci-endpoint.txt to reST
  Documentation: PCI: convert pcieaer-howto.txt to reST
  Documentation: PCI: convert pci-error-recovery.txt to reST
  Documentation: PCI: convert acpi-info.txt to reST
  Documentation: PCI: convert MSI-HOWTO.txt to reST
  Documentation: PCI: convert pci-iov-howto.txt to reST
  Documentation: PCI: convert PCIEBUS-HOWTO.txt to reST
  Documentation: PCI: convert pci.txt to reST
  Documentation: add Linux PCI to Sphinx TOC tree

Many NVIDIA GPUs can be configured as either a single-function video device
or a multi-function device with video at function 0 and an HDA audio
controller at function 1.  The HDA controller can be enabled or disabled by
a bit in the function 0 config space.

Some BIOSes leave the HDA disabled, which means the HDMI connector from the
NVIDIA GPU may not work.  Sometimes the BIOS enables the HDA if an HDMI
cable is connected at boot time, but that doesn't handle hotplug cases.

Enable the HDA controller on device enumeration and resume and re-read the
header type, which tells us whether the GPU is a multi-function device.

This quirk is limited to NVIDIA PCI devices with the VGA Controller device
class.  This is expected to correspond to product configurations where the
NVIDIA GPU has connectors attached.  Other products where the device class
is 3D Controller are expected to correspond to configurations where the
NVIDIA GPU is dedicated (dGPU) and has no connectors.  See original post
(URL below) for more details.

This commit takes inspiration from an earlier patch by Daniel Drake.

Link: https://lore.kernel.org/r/20190708051744.24039-1-drake@endlessm.com v2
Link: https://lore.kernel.org/r/20190613063514.15317-1-drake@endlessm.com v1
Link: https://devtalk.nvidia.com/default/topic/1024022
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75985Signed-off-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Daniel Drake <drake@endlessm.com>
[bhelgaas: commit log, log message, return early if already enabled]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Aaron Plattner <aplattner@nvidia.com>
Cc: Peter Wu <peter@lekensteyn.nl>
Cc: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: Karol Herbst <kherbst@redhat.com>
Cc: Maik Freudenberg <hhfeuer@gmx.de>

The commit c9a70787 ("tools pci: Do not delete pcitest.sh in 'make clean'")
fixed a `make tools clean` issue and simultaneously brought a regression
to the installation process:

  for script in .../tools/pci/pcitest.sh; do	\
	install $script .../usr/usr/bin;	\
  done
  install: cannot stat '.../tools/pci/pcitest.sh': No such file or directory

Update the install commands to fix the remaining issue.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Jean-Jacques Hiblot <jjhiblot@ti.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>

If CONFIG_GPIOLIB is not selected the compilation results in the
following build errors:

drivers/pci/controller/dwc/pci-dra7xx.c:
 In function dra7xx_pcie_probe:
drivers/pci/controller/dwc/pci-dra7xx.c:777:10:
 error: implicit declaration of function devm_gpiod_get_optional;
 did you mean devm_regulator_get_optional? [-Werror=implicit-function-declaration]

  reset = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH);

drivers/pci/controller/dwc/pci-dra7xx.c:778:45: error: ‘GPIOD_OUT_HIGH’
undeclared (first use in this function); did you mean ‘GPIOF_INIT_HIGH’?
  reset = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH);
                                             ^~~~~~~~~~~~~~
                                             GPIOF_INIT_HIGH

Fix them by including the appropriate header file.
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
[lorenzo.pieralisi@arm.com: commit log]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>

Fix typos in drivers/pci.  Comment and whitespace changes only.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Reviewed-by: Randy Dunlap <rdunlap@infradead.org>

The current INTx handling function clears all interrupts after
handling the first pending; this can potentially cause missing INTx
detection. Fix the code to clear only the handled INTx IRQ.

Fixes: 9af6bcb1 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver")
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
Acked-by: Karthikeyan Mitran <m.karthikeyan@mobiveil.co.in>
Tested-by: Karthikeyan Mitran <m.karthikeyan@mobiveil.co.in>

In the loop handling INTx interrupts in mobiveil_pcie_isr(), there is
no code to update the loop control variable, which is causing an
infinite loop.

Fix the code by reading the interrupt status registers inside the
loop.

Fixes: 9af6bcb1 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver")
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
Acked-by: Karthikeyan Mitran <m.karthikeyan@mobiveil.co.in>
Tested-by: Karthikeyan Mitran <m.karthikeyan@mobiveil.co.in>

Move the PCIe PIO master enablement to function mobiveil_host_init().
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>

Current code erroneously sets-up the lower 32-bit PCI base address in
the inbound window, which results in inbound transactions not working in
64-bit platforms.

Fixes: 9af6bcb1 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver")
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>

Current code erroneously sets-up only the lower 32-bit CPU base address
in the  outbound window, which results in outbound transactions not
working in 64-bit platforms.

Fix it.

Fixes: 9af6bcb1 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver")
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>

The lower 10 bits of window size field are hardcoded to zero in HW so
they can't really be changed but the lower 10-bit of PAB_AXI_AMAP_CTRL
register are used for control fields, so while programming inbound and
outbout windows decoding we should mask out the lower 10-bit of window
size to prevent overriding the control bits.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>

While programming the inbound and outbound windows in

program_{ib/ob}_windows()

we shoud clear the control fields in the registers before programming
it with a new value to prevent stale bits from older configuration.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>

Current code only keeps track of the number of outbound windows
configured but it does not for inbound windows. Add a counter
to keep track of initialized inbound windows.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>

In program_ib/ob_windows() check the window index from the function
parameter instead of the total number of initialized windows to
determine if the specified window is valid.

Fixes: 9af6bcb1 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver")
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>

In function program_ob_windows(), remove the redundant read
operations to registers PAB_AXI_AMAP_AXI_WIN and PAB_AXI_AMAP_PEX_WIN_H,
and remove the useless definition of 'value'. Rename the parameter
'config_io_bit' to 'type' and then remove the definition of 'type'.

In function program_ib_windows(), remove the definitions of
'pio_ctrl_val' and 'amap_ctrl_dw' and reduce to only one variable
'value' to keep the temporary value read from registers.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>

The memory for the host controller private structure (struct
mobiveil_pcie) is allocated together with the pci_host_bridge structure
in function devm_pci_alloc_host_bridge(), so it is unnecessary to check
the return value when get the private structure pointer.

Remove the useless check.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>

Some error return values in the host controller driver are
either unconventional or plain wrong. Update them all with
the expected return values.
Signed-off-by: Hou Zhiqiang <Zhinqiang.Hou@nxp.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>

Move the resource type check into an if/else block and only
set-up the outbound window for MEM and IO resource. No functional
change intended.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>

To make some register updates more readable use a temporary
value to hold the register value and carry out the update.

Change the register update sequence to:

- Read out the original value from the target register
- Update the value
- Program the updated value back to the register
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>

Reformat the code to make it more readable. No functional
change intended.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>

Change the "gpio_slave" and "apb_csr" to optional, the "gpio_slave"
is not used in current code, and "apb_csr" is not used by some platforms.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>

Current check for devfn number in mobiveil_pci_valid_device() is
wrong in that it flags as invalid functions present in PCI device 0
in the root bus while it is perfectly valid to access all functions
in PCI device 0 in the root bus.

Update the check in mobiveil_pci_valid_device() to fix the issue.

Fixes: 9af6bcb1 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver")
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>

The reset value of Primary, Secondary and Subordinate bus numbers is
zero which is a broken setup.

Program a sensible default value for Primary/Secondary/Subordinate
bus numbers.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>