- 11 Jan, 2012 7 commits
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Ralf Baechle authored
Merge branches 'next/ar7', 'next/ath79', 'next/bcm63xx', 'next/bmips', 'next/cavium', 'next/generic', 'next/kprobes', 'next/lantiq', 'next/perf' and 'next/raza' into mips-for-linux-next
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Ralf Baechle authored
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Ralf Baechle authored
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Ralf Baechle authored
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Ralf Baechle authored
Only available for R4000 style TLBs anyway and proper ordering of initialization code made this crude interface unncecessary. Signed-off-by:Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
On MIPS the generic PCI code has always defaulted to L1_CACHE_BYTES because the architecutre PCI code did not provide a better default. In particular on systems with S-caches or T-caches this was suboptimal. Provide a better default by setting pci_dfl_cache_line_size based on the size of the line size of the lowest level of the cache hierarchy. Signed-off-by:
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Hillf Danton authored
When flushing TLB, if @vma is backed by huge page, we could flush huge TLB, due to that huge page is defined to be far from normal page. Signed-off-by:
Hillf Danton <dhillf@gmail.com> Acked-by:
David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: "Jayachandran C." <jayachandranc@netlogicmicro.com> Patchwork: https://patchwork.linux-mips.org/patch/2825/Signed-off-by:
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- 08 Dec, 2011 13 commits
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Chandrakala Chavva authored
Only 64-bit kernels are supported, no need for SYS_SUPPORTS_HIGHMEM Signed-off-by:
Chandrakala Chavva <cchavva@caviumnetworks.com> Signed-off-by:
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David Daney authored
OCTEON II SOCs have a different PCIe implementation than is present in OCTEON Plus. Signed-off-by:
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David Daney authored
Signed-off-by:
David Daney <ddaney@caviumnetworks.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2987/ Patchwork: https://patchwork.linux-mips.org/patch/3161/Signed-off-by:
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Manuel Lauss authored
Signed-off-by:
Manuel Lauss <manuel.lauss@googlemail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3006/Signed-off-by:
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Manuel Lauss authored
The PB1200 has the CPLD located at an address which on the DB1200 is RAM; reading the Board-ID sometimes results in a PB1200 being detected instead (especially during reboots after long uptimes). On the other hand, the address of the DB1200's CPLD is hosting Flash chips on the PB1200. Test for the DB1200 first and additionally do a quick write-test to the hexleds register to make sure we're writing to the CPLD. Signed-off-by:
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Manuel Lauss authored
With a generic plat_irq_dispatch (for Alchemy at least) code for both interrupt controller types can coexist in a single kernel image and be autodetected at runtime. Signed-off-by:
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Manuel Lauss authored
IC and GPIC are now chain handlers of the traditional MIPS IRQ controller. Signed-off-by:
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Manuel Lauss authored
No need for a device_initcall. Signed-off-by:
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Manuel Lauss authored
Wire up the ADS7846 touchscreen controller on the DB1100. Signed-off-by:
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Manuel Lauss authored
Add necessary transceiver control platform data and hook up the IrDA peripheral on the DB1000 and DB1100 boards. Signed-off-by:
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Manuel Lauss authored
Moderate driver cleanup: convert to platform driver, get rid of board-specific code. Driver loads and runs on a DB1100 board. But since I have no other IrDA hardware to exchange data with I can't say whether it really sends and receives. Signed-off-by:
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Manuel Lauss authored
The information in those headers is no longer necessary. Signed-off-by:
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Manuel Lauss authored
Transform the au1550nd.c driver into a platform_driver and hook it up in the PB1550 board (gen_nand works fine on the DB1550, but since I don't have a PB1550 to test this driver stays for now). Signed-off-by:
Artem Bityutskiy <dedekind1@gmail.com> Signed-off-by:
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- 07 Dec, 2011 20 commits
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Hillf Danton authored
Netlogic XLR chip has multiple cores. Each core includes four integrated hardware threads, and they share L1 data and instruction caches. If the chip is marked to be SMT capable, scheduler then could do more, say, idle load balancing. Changes are now confined only to the code of XLR, and hardware is probed to get core ID for correct setup. [jayachandranc: simplified and adapted for new merged XLR/XLP code] Signed-off-by:
Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2972/Signed-off-by:
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Jayachandran C authored
Add new processor ID to asm/cpu.h and kernel/cpu-probe.c. Update to new CPU frequency detection code which works on XLP 3XX and 8XX. Signed-off-by:
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Jayachandran C authored
Create a common NMI and reset handler in smpboot.S and use this for both XLR and XLP. In the earlier code, the woken up CPUs would busy wait until released, switch this to wakeup by NMI. The initial wakeup code or XLR and XLP are differ since they are started from different bootloaders (XLP from u-boot and XLR from netlogic bootloader). But in both platforms the woken up CPUs wait and are released by sending an NMI. Add support for starting XLR and XLP in 1/2/4 threads per core. Signed-off-by:
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Jayachandran C authored
Signed-off-by:
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Jayachandran C authored
- Add CPU_XLP and NLM_XLR_BOARD to arch/mips/Kconfig for Netlogic XLP boards - Update mips Makefiles to add XLP Signed-off-by:
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Jayachandran C authored
- Update common files to support XLP. - Add arch/mips/include/asm/netlogic/xlp-hal for register definitions and access macros - Add arch/mips/netlogic/xlp/ for XLP specific files. Signed-off-by:
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Jayachandran C authored
Add support for Netlogic's XLP MIPS SoC. This patch adds: * XLP processor ID in cpu_probe.c and asm/cpu.h * XLP case to asm/module.h * CPU_XLP case to mm/tlbex.c * minor change to r4k cache handling to ignore XLP secondary cache * XLP cpu overrides to mach-netlogic/cpu-feature-overrides.h Signed-off-by:
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Jayachandran C authored
- Enable PCI and MSI by default - Update cross compile tool-chain and rootfs Signed-off-by:
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Jayachandran C authored
- Move code that can be shared with XLP (irq.c, smp.c, time.c and xlr_console.c) to arch/mips/netlogic/common - Add asm/netlogic/haldefs.h and asm/netlogic/common.h for common and io functions shared with XLP - remove type 'nlm_reg_t *' and use uint64_t for mmio offsets - Move XLR specific code in smp.c to xlr/wakeup.c - Move XLR specific PCI code from irq.c to mips/pci/pci-xlr.c - Provide API for pic functions called from common/irq.c Signed-off-by:
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Jayachandran C authored
The -Werror compilation flag is already set for arch/mips - it can be removed from arch/mips/xlr/Makefile Signed-off-by:
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Jayachandran C authored
The CPU_XLR config variable is sufficient for XLR compilation, the variable NLM_XLR can be removed. Signed-off-by:
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Jayachandran C authored
- Use platform- variable for xlr - Load address common for all netlogic chips Signed-off-by:
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Ganesan Ramalingam authored
Add basic support for MSI. Signed-off-by:
Ganesan Ramalingam <ganesanr@netlogicmicro.com> Signed-off-by:
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Jayachandran C authored
XLR dcache is fully coherent across CPUs, so avoid unnecessary dcache flushes. Signed-off-by:
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Jayachandran C authored
Use r4k_wait as the CPU wait function for XLR/XLS processors. Signed-off-by:
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Jayachandran C authored
Move load address from 0x84000000 to 0x80100000 to avoid wasting memory. Signed-off-by:
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Deng-Cheng Zhu authored
Simplify the code by changing the place of event->destroy(). Signed-off-by:
Deng-Cheng Zhu <dczhu@mips.com> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Paul Mackerras <paulus@samba.org> Cc: Ingo Molnar <mingo@elte.hu> Cc: Arnaldo Carvalho de Melo <acme@ghostprotocols.net> Cc: David Daney <david.daney@cavium.com> Cc: Eyal Barzilay <eyal@mips.com> Cc: Zenon Fortuna <zenon@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/3109/Signed-off-by:
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Deng-Cheng Zhu authored
Why removing pmu checking: Since 3.2-rc1, when arch level event init is called, the event is already connected to its PMU. Also, validate_event() is _only_ called by validate_group() in event init, so there is no need of checking or temporarily assigning event pmu during validate_group(). Why removing event state checking: Events could be created in PERF_EVENT_STATE_OFF (attr->disabled == 1), when these events go through this checking, validate_group() does dummy work. But we do need to do group scheduling emulation for them in event init. Again, validate_event() is _only_ called by validate_group(). Reference: http://www.spinics.net/lists/mips/msg42190.htmlSigned-off-by:
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Deng-Cheng Zhu authored
Port the following patch for ARM by Mark Rutland: - 57ce9bb3 ARM: 6902/1: perf: Remove erroneous check on active_events When initialising a PMU, there is a check to protect against races with other CPUs filling all of the available event slots. Since armpmu_add checks that an event can be scheduled, we do not need to do this at initialisation time. Furthermore the current code is broken because it assumes that atomic_inc_not_zero will unconditionally increment active_counts and then tries to decrement it again on failure. This patch removes the broken, redundant code. Signed-off-by:
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Deng-Cheng Zhu authored
MIPS licensees may want to modify performance counters to count extra events. Also, now that the user is working on raw events, the manual is being used for sure. And feeding unsupported events shouldn't cause hardware failure and the like. [ralf@linux-mips.org: performance events also being used in internal performance evaluation and have a tendency to change as the micro- architecture evolves, even for minor revisions that may not be distinguishable by PrID. It's not very practicable to maintain a list of all events and there is no real benefit.] Signed-off-by:
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