- 30 Mar, 2015 18 commits
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Stefan Agner authored
The anyway depricated gpio-range-cells property was never used by the pin controller driver. This patch removes it. Signed-off-by:
Stefan Agner <stefan@agner.ch> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Marc Zyngier authored
IMX6 has been (ab)using the gic_arch_extn to provide wakeup from suspend, and it makes a lot of sense to convert this code to use stacked domains instead. This patch does just this, updating the DT files to actually reflect what the HW provides. BIG FAT WARNING: because the DTs were so far lying by not exposing the fact that the GPC block is actually the first interrupt controller in the chain, kernels with this patch applied wont have any suspend-resume facility when booted with old DTs, and old kernels with updated DTs won't even boot. Tested-by:
Marc Zyngier <marc.zyngier@arm.com> Signed-off-by:
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Fabio Estevam authored
Add support for the CLAA057VC01CW display. Signed-off-by:
Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by:
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Uwe Kleine-König authored
Add some defines currently missing, fix ordering to make the list sorted by (mux_reg, mux_val), make sure pins are grouped by mux_reg. The same definitions are missing from the old pinmux header (arch/arm/mach-imx/iomux-mx25.h) but as only legacy machine support uses that and therefor the existing list is obviously good enough I didn't spend the effort to add the corresponding definitions there, too. Signed-off-by:
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by:
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Uwe Kleine-König authored
Noticed while looking over the pad definitions. None of the bogus definitions is used in-tree. Signed-off-by:
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Markus Pargmann authored
It may be useful to disable the internal rtc snvs-rtc because an external rtc is available. This patch adds a label so that board files can disable this rtc. Signed-off-by:
Markus Pargmann <mpa@pengutronix.de> Signed-off-by:
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Gwenhael Goavec-Merou authored
Signed-off-by:
Gwenhael Goavec-Merou <gwenhael.goavec-merou@armadeus.com> Signed-off-by:
Sebastien Szymanski <sebastien.szymanski@armadeus.com> Signed-off-by:
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Gwenhael Goavec-Merou authored
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Gwenhael Goavec-Merou authored
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Gwenhael Goavec-Merou authored
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Gwenhael Goavec-Merou authored
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Liu Ying authored
The MIPI DSI node contains some ports which represent possible DRM CRTCs it can connect with. Each port has a 'reg' property embedded. This property will be wrongly interpretted by the MIPI DSI bus driver, because the driver will take each subnode which contains a 'reg' property as a DSI peripheral device. This patch moves the existing MIPI DSI ports into a new 'ports' node so that the MIPI DSI bus driver may distinguish its DSI peripheral device(s) from the existing ports. Acked-by:
Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by:
Liu Ying <Ying.Liu@freescale.com> Signed-off-by:
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Peter Chen authored
Since imx6sx-sdb reva board is experimental and will not be used formally (eg, no software release based on it), we set revb board as the formal imx6sx-sdb board. The imx6sx-sdb uses pfuse200 as pmic which has only one power supply for both VDDARM_IN and VDDSOC_IN, so VDDARM_IN and VDDSOC_IN have to use the same (higher one in the same frequency) one as its power supply, that's the reason we override the OPP setting in board dts file. Signed-off-by:
Peter Chen <peter.chen@freescale.com> Signed-off-by:
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Peter Chen authored
The imx6sx sdb board has two revisions, the current mainline one is reva which is experimental and mainly for internal use. In this commit, we rename imx6sx-sdb.dts to imx6sx-sdb.dtsi, and move the reva dedicated contents to imx6sx-sdb-reva.dts. Signed-off-by:
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Bhuvanchandra DV authored
MCP2515 CAN controller is available on Colibri Evaluation board. Hence enable MCP2515 CAN. Acked-by:
Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Signed-off-by:
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Bhuvanchandra DV authored
Signed-off-by:
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Shawn Guo authored
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Shawn Guo authored
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- 13 Mar, 2015 7 commits
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Fabio Estevam authored
We do not have CONFIG_MACH_MX25_3DS platform anymore, so update the defconfig. Signed-off-by:
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Fabio Estevam authored
platform-imxdi_rtc.c is only used by mx25, so it can safely go away now that mx25 has been converted to dt. Signed-off-by:
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Fabio Estevam authored
As mx25 has been converted to a dt-only platform, we do not need the "mx25.h" header file anymore. Remove it and also clean up all the mx25 occurences from the platform helper code. Signed-off-by:
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Fabio Estevam authored
We use dynamic memory mapping when using dt, so remove all the static mappings. Signed-off-by:
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Fabio Estevam authored
We should use dt to retrieve the IIM base address. Signed-off-by:
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Fabio Estevam authored
mx25_clocks_init() is only used to register the clocks for non-dt platforms. As mx25 has been converted to a dt-only platform, we can safely remove it. Signed-off-by:
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Stefan Agner authored
Depend the MXC debug board on machines which actually support it. Signed-off-by:
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- 11 Mar, 2015 5 commits
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Fabio Estevam authored
As mx25 is a dt-only platform, we can get rid of platform code support files, which are unused now. Signed-off-by:
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Fabio Estevam authored
As there is no more mx25 board files, we can turn mx25 into a dt-only platform. Rename imx25-dt.c to mach-imx25.c to be consistent with the other i.MX SoCs. Signed-off-by:
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Fabio Estevam authored
eukrea mx25 is well supported in device tree, so let's get rid of its board files. Cc: Eric Bénard <eric@eukrea.com> Signed-off-by:
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Philipp Zabel authored
When generic pm domain support is enabled, the PGC can be used to completely gate power to the PU power domain containing GPU3D, GPU2D, and VPU cores. This code triggers the PGC powerdown sequence to disable the GPU/VPU isolation cells and gate power and then disables the PU regulator. To reenable, the reverse powerup sequence is triggered after the PU regulator is enabled again. The GPU and VPU devices in the PU power domain temporarily need to be clocked during powerup, so that the reset machinery can work. [Avoid explicit regulator enabling in probe, unless !PM] Signed-off-by:
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Philipp Zabel authored
The i.MX6 contains a power controller that controls power gating and sequencing for the SoC's power domains. Signed-off-by:
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- 08 Mar, 2015 2 commits
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Stefan Agner authored
Add binding documentation for CPU configuration and interrupt router submodule of the Miscellaneous System Control Module. The MSCM is used in all variants of Freescale Vybrid SoC's. Acked-by:
Jason Cooper <jason@lakedaemon.net>
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Stefan Agner authored
This adds support for Vybrid's interrupt router. On VF6xx models, almost all peripherals can be used by either of the two CPU's, the Cortex-A5 or the Cortex-M4. The interrupt router routes the peripheral interrupts to the configured CPU. This IRQ chip driver configures the interrupt router to route the requested interrupt to the CPU the kernel is running on. The driver makes use of the irqdomain hierarchy support. The parent is given by the device tree. This should be one of the two possible parents either ARM GIC or the ARM NVIC interrupt controller. The latter is currently not yet supported. Note that there is no resource control mechnism implemented to avoid concurrent access of the same peripheral. The user needs to make sure to use device trees which assign the peripherals orthogonally. However, this driver warns the user in case the interrupt is already configured for the other CPU. This provides a poor man's resource controller. Acked-by:
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- 06 Mar, 2015 1 commit
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Fabio Estevam authored
imx25-pdk.dts provides a more complete support than the board file version, so let's get rid of the board file. Signed-off-by:
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- 03 Mar, 2015 3 commits
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Yannick Guerrini authored
change 'mutliple' to 'multiple' Signed-off-by:
Yannick Guerrini <yguerrini@tomshardware.fr> Signed-off-by:
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Fabio Estevam authored
Use "This enables" in the Kconfig help text to fix grammar. Signed-off-by:
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Uwe Kleine-König authored
Also fix all machine files to make use of it and while at it also make the pad lists __initconst. Signed-off-by:
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- 02 Mar, 2015 4 commits
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Alison Chaiken authored
Probe all children of the WEIM node, reporting any failures. Report failure from parsing of WEIM node itself if probes of all children fail. Signed-off-by:
Alison Chaiken <alison_chaiken@mentor.com> Acked-by:
Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by:
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Liu Ying authored
The CG8 field of the CCM CCGR3 register is the 'mipi_core_cfg' gate clock, according to the i.MX6q/sdl reference manuals. This clock is actually the gate for several clocks, including the ipg clock's output. The MIPI DSI host controller embedded in the i.MX6q/sdl SoCs takes the ipg clock as the pclk - the APB clock signal . In order to gate/ungate the ipg clock, this patch adds a new shared clock gate named as "mipi_ipg". Signed-off-by:
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Liu Ying authored
The CG8 field of the CCM CCGR3 register is named as 'mipi_core_cfg' clock, according to the i.MX6q/sdl reference manuals. This clock is actually the gate for several clocks, including the hsi_tx_sel clock's output and the video_27m clock's output. The MIPI DSI host controller embedded in the i.MX6q/sdl SoCs uses the video_27m clock to generate PLL reference clock and MIPI core configuration clock. In order to gate/ungate the two MIPI DSI host controller relevant clocks, this patch adds the mipi_core_cfg clock as a shared clock gate. Suggested-by:
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Liu Ying authored
The CG8 field of the CCM CCGR3 register is named as 'mipi_core_cfg' clock, according to the i.MX6q/sdl reference manuals. This clock is actually the gate for several clocks, including the hsi_tx_sel clock's output and the video_27m clock's output. So, this patch changes the hsi_tx clock to be a shared clock gate. Suggested-by:
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