- 18 Dec, 2019 40 commits
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Jane Jian authored
Use MMSCH V1 to finish Memory Controller programming as well as start MMSCH to do VCN2.5 initialization. Signed-off-by:
Jane Jian <Jane.Jian@amd.com> Reviewed-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Jane Jian authored
Use MMSCH to do the initialization since MMSCH manages VCN2.5 instances and its world switch. Signed-off-by:
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Guchun Chen authored
Code refactor and no functional change. Fixes: 4cf781c2 ("drm/amdgpu: Added RAS UMC error query support for Arcturus") Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
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Alex Deucher authored
For udelay. This is needed for some platforms. Reviewed-by:
Nicholas Kazlauskas <nicholas.kazluaskas@amd.com> Signed-off-by:
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Alex Deucher authored
To protect access to the metrics table. v2: unlock on error Bug: https://gitlab.freedesktop.org/drm/amd/issues/900Reviewed-by:
Kevin Wang <kevin1.wang@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Alex Deucher authored
To protect access to the metrics table. v2: unlock on error Bug: https://gitlab.freedesktop.org/drm/amd/issues/900Reviewed-by:
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Alex Deucher authored
To protect access to the metrics table. v2: unlock on error Bug: https://gitlab.freedesktop.org/drm/amd/issues/900Reviewed-by:
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Alex Deucher authored
To protect access to the metrics table. v2: unlock on error Bug: https://gitlab.freedesktop.org/drm/amd/issues/900Reviewed-by:
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Alex Deucher authored
This table is used for lots of things, add it's own lock. Bug: https://gitlab.freedesktop.org/drm/amd/issues/900Reviewed-by:
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Pan Zhang authored
this set adds support for removal of gpu drm dead code. patch3 is similar with patch 1: `num` is a data of u8 type and ATOM_MAX_HW_I2C_READ == 255, so there is a impossible condition '(num > 255) => (0-255 > 255)'. Signed-off-by:
Pan Zhang <zhangpan26@huawei.com> Signed-off-by:
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Alex Deucher authored
Add a safety check to runtime suspend to make sure all outstanding fences have signaled before we suspend. Doesn't fix any known issue. We already do this via the fence driver suspend function, but we just force completion rather than bailing. This bails on runtime suspend so we can try again later once the fences are signaled to avoid missing any outstanding work. Reviewed-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
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Alex Deucher authored
s/dispaly/display/g Reviewed-by:
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Andrey Grodzovsky authored
This is to avoid queueing jobs to same CPU during XGMI hive reset because there is a strict timeline for when the reset commands must reach all the GPUs in the hive. Signed-off-by:
Le Ma <Le.Ma@amd.com> Signed-off-by:
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Andrey Grodzovsky authored
Use task barrier in XGMI hive to synchronize ASIC resets across devices in XGMI hive. v2: Return right away with a warning if no xgmi hive, update doc. Signed-off-by:
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Andrey Grodzovsky authored
Signed-off-by:
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Andrey Grodzovsky authored
It is used to synchronize N threads at a rendevouz point before execution of critical code that has to be started by all the threads at approximatly the same time. v2: Remove mention of reset use case, improve doc. Signed-off-by:
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Andrey Grodzovsky authored
In preparation for doing XGMI reset synchronization using task barrier. Signed-off-by:
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Leo Liu authored
Esp. VCN1.0 headers should not be here v2: add back the <linux/module.h> to keep consistent. Signed-off-by:
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Monk Liu authored
issues: MEC is ruined by the amdkfd_pre_reset after VF FLR done fix: amdkfd_pre_reset() would ruin MEC after hypervisor finished the VF FLR, the correct sequence is do amdkfd_pre_reset before VF FLR but there is a limitation to block this sequence: if we do pre_reset() before VF FLR, it would go KIQ way to do register access and stuck there, because KIQ probably won't work by that time (e.g. you already made GFX hang) so the best way right now is to simply remove it. Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
Emily Deng <Emily.Deng@amd.com> Signed-off-by:
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Monk Liu authored
issues: gpu_recover() is re-entered by the mailbox interrupt handler mxgpu_nv.c fix: we need to bypass the gpu_recover() invoke in mailbox interrupt as long as the timeout is not infinite (thus the TDR will be triggered automatically after time out, no need to invoke gpu_recover() through mailbox interrupt. Signed-off-by:
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Yintian Tao authored
Under sriov pp one vf mode, there is no need to set soc clk under pp one vf because smu firmware will depend on the mclk to set the appropriate soc clk for it. Signed-off-by:
Yintian Tao <yttao@amd.com> Reviewed-by : Monk Liu <monk.liu@amd.com> Signed-off-by:
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Nirmoy Das authored
entity should not keep copy and maintain sched list for itself. Signed-off-by:
Nirmoy Das <nirmoy.das@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Nirmoy Das authored
This sched array can be passed on to entity creation routine instead of manually creating such sched array on every context creation. v2: squash in missing break fix Signed-off-by:
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Nirmoy Das authored
drm_sched_entity_init() takes drm gpu scheduler list instead of drm_sched_rq list. This makes conversion of drm_sched_rq list to drm gpu scheduler list unnecessary Signed-off-by:
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Nirmoy Das authored
Entity currently keeps a copy of run_queue list and modify it in drm_sched_entity_set_priority(). Entities shouldn't modify run_queue list. Use drm_gpu_scheduler list instead of drm_sched_rq list in drm_sched_entity struct. In this way we can select a runqueue based on entity/ctx's priority for a drm scheduler. Signed-off-by:
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Alex Deucher authored
Increment the usage count in emit fence, and decrement in process fence to make sure the GPU is always considered in use while there are fences outstanding. We always wait for the engines to drain in runtime suspend, but in practice that only covers short lived jobs for gfx. This should cover us for longer lived fences. Reviewed-by:
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Zhan Liu authored
[Why] SMU watermark table (WMTABLE) validity check is missing on Renoir. This validity check is very useful for checking whether WMTABLE is updated successfully. [How] Add SMU watermark validity check. Signed-off-by:
Zhan Liu <zhan.liu@amd.com> Reviewed-by:
Hersen Wu <hersenxs.wu@amd.com> Signed-off-by:
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zhengbin authored
Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:318:2-3: Unneeded semicolon Reported-by:
Hulk Robot <hulkci@huawei.com> Signed-off-by:
zhengbin <zhengbin13@huawei.com> Signed-off-by:
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zhengbin authored
Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c:1967:2-3: Unneeded semicolon Reported-by:
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zhengbin authored
Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c:110:3-4: Unneeded semicolon drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c:133:2-3: Unneeded semicolon drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c:163:2-3: Unneeded semicolon drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c:191:2-3: Unneeded semicolon Reported-by:
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zhengbin authored
Fixes coccicheck warning: drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c:412:90-91: Unneeded semicolon Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Reported-by:
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Alex Deucher authored
We already did this for older generations. Reviewed-by:
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Alex Deucher authored
We already did this for older generations. Reviewed-by:
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Nikola Cornij authored
[why] It's required for debug purposes. [how] Add a dsc_bpp_increment_div debug option that overrides DPCD BITS_PER_PIXEL_INCREMENT value. The value dsc_bpp_increment_div should be set to is the one after parsing, i.e. it could be 1, 2, 4, 8 or 16 (meaning 1pix, 1/2pix, ..., 1/16pix). Signed-off-by:
Nikola Cornij <nikola.cornij@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Anthony Koo authored
[Why] eDP is internal link and link loss is unexpected. It is typically going to be PSR related errors, which is handled separately. [How] Check for eDP and skip check for link loss Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
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Samson Tam authored
[Why] Cursor disappears for some SLS displays that are rotated 180 and 270 degrees. This occurs when there is no pipe split being done ( ex. 3 or more displays ). The cursor calculations assume pipe splitting is done so when it calculates the new cursor position in hwss.set_cursor_position(), it is out-of-bounds so it disables the cursor in hubp.set_cursor_position(). [How] In non pipe split cases, calculate cursor using viewport size ( width or height ) instead of viewport size * 2 ( the two because pipe splitting divides the rectangle into two ). Signed-off-by:
Samson Tam <Samson.Tam@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Sung Lee authored
[Why] Previous formula for calculating DPP CLK DTO was hard to understand. [How] Replace with easier to understand formula that produces same results. Signed-off-by:
Sung Lee <sung.lee@amd.com> Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
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Sung Lee authored
[Why] A corner case currently exists where DPP DTO is lowered before pipes are updated to a higher viewport. This causes underflow as the DPPCLK is too low for the current viewport. [How] Only lower DPP DTO when it is safe to lower, or if the newer clocks are higher than the current ones. Signed-off-by:
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Jun Lei authored
[why] DAL3 should support SRIOV [how] Add support for the virtual dal flag. This flag should skip most/all of DC construction since the HW isn't accessible, but still construct WindowsDM (almost) normally but with only SW display targets Signed-off-by:
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Aric Cyr authored
Fix manual trigger source correctly be TRIGA for DCN2 rather than MANUAL_FLOW. Signed-off-by:
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