- 30 Mar, 2017 40 commits
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Andrew F. Davis authored
Found with scripts/coccinelle/misc/boolconv.cocci. Signed-off-by:
Andrew F. Davis <afd@ti.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Andres Rodriguez authored
This helps de-duplicate a long expression and removes overly long lines. v2: Rename macro and undef it Reviewed-by:
Andres Rodriguez <andresx7@gmail.com> Signed-off-by:
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Andres Rodriguez authored
Fence data is easier to read and allows us to correlate to identify corresponding dma_fence ftrace events. Reviewed-by:
Chunming Zhou <david1.zhou@amd.com> Reviewed-by:
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Andres Rodriguez authored
Remove pointers which provide redundant information which is already easier to deduce from other fields. Reviewed-by:
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Andres Rodriguez authored
Pointers get reallocated and they are hard to read for humans. Use ids instead. Reviewed-by:
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Andres Rodriguez authored
Consistent formatting makes it easier to read the logs and apply simple awk oneliners. I missed some of these on my last patch. Reviewed-by:
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Andres Rodriguez authored
A unique id is useful for debugging and tracing. Intended to replace pointers in ftrace output. Reviewed-by:
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Roger.He authored
We originally limited the IH to 4k on tonga since it uses bus addresses directly rather than GPU MC addresses, so it needs contigous physical memory. This brings it inline with other asics. Signed-off-by:
Roger.He <Hongbo.He@amd.com> Acked-by:
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Alex Deucher authored
SI cards don't expose GDS as a separate pool. The CP manages GDS and the UMDs use special CP packets to allocate GDS memory. v2: drop extra whitespace change bug: https://bugzilla.kernel.org/show_bug.cgi?id=194867Reviewed-by:
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Alex Deucher authored
Leftover from gfx7 code. gfx6 never sets up the gds buffers in the first place. Reviewed-by:
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Rex Zhu authored
fix logic error in hw_fini and set_clockgating_state functions. Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Reviewed-by:
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Rex Zhu authored
start vce first then enable vce dpm. Signed-off-by:
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Alex Deucher authored
Used for fetching external GPU information. Signed-off-by: -
Alex Deucher authored
Used for fetching external GPU information. Signed-off-by: -
Leo Liu authored
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Leo Liu <leo.liu@amd.com> Reviewed-by:
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Leo Liu authored
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Leo Liu authored
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Leo Liu authored
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Leo Liu authored
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Leo Liu authored
And initialize them Reviewed-by:
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Leo Liu authored
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Leo Liu authored
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Leo Liu authored
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Huang Rui authored
Acked-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
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Huang Rui authored
Acked-by:
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Alex Deucher authored
Newer asics use different registers so abstract it. Reviewed-by:
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Rex Zhu authored
v2: agd: integrate Christian's comments. v3: print error message if call fails Reviewed-by:
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Alex Xie authored
This lets each asic set whichever flags it supports. Signed-off-by:
Alex Xie <AlexBin.Xie@amd.com> Reviewed-by:
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Alex Xie authored
Set asic specific gart pte flags in the gmc IP module for each asic. Signed-off-by:
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Huang Rui authored
This will be used for newer asics. Acked-by:
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Chunming Zhou authored
Necessary for new asics. Signed-off-by:
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Alex Deucher authored
The contextID field (formerly known as src_data) of the IH vector stores client specific information about an interrupt. It was expanded from 32 bits to 128 on newer asics. Expand the src_id field to handle this. Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Reviewed-by:
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Alex Deucher authored
Newer asics have a two levels of irq ids now: client id - the IP src id - the interrupt src within the IP v2: integrated Christian's comments. v3: fix rebase fail in SI and CIK Signed-off-by:
Ken Wang <Qingqing.Wang@amd.com> Reviewed-by:
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Ken Wang authored
Newer asics need 64 bit doorbells. v2: fix comment (Nils) Reviewed-by:
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Ken Wang authored
Newer asics need 64 bit writeback slots. Reviewed-by:
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Ken Wang authored
Newer asics need 64 bit wptrs. If the wptr is now smaller than the rptr that doesn't indicate a wrap-around anymore. v2: integrate Christian's comments. Signed-off-by:
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Junwei Zhang authored
v2: agd: move apertures to mc structure Signed-off-by:
Flora Cui <Flora.Cui@amd.com> Reviewed-by:
Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by:
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Daniel Vetter authored
Again no apparent explanation for the split except hysterical raisins. Merging them also makes it a bit more obviuos what's going on wrt the runtime pm refdancing. Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: amd-gfx@lists.freedesktop.org Reviewed-by:
Daniel Vetter <daniel.vetter@intel.com> Signed-off-by:
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Daniel Vetter authored
Again no apparent explanation for the split except hysterical raisins. Merging them also makes it a bit more obviuos what's going on wrt the runtime pm refdancing. Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: amd-gfx@lists.freedesktop.org Reviewed-by:
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Andres Rodriguez authored
This information is intended to provide the required data to associate amdgpu tracepoints with their corresponding dma_fence_* events. Reviewed-by:
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