- 30 Sep, 2015 40 commits
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Arun Siluvery authored
Signed-off-by:
Arun Siluvery <arun.siluvery@linux.intel.com> Reviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Arun Siluvery authored
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Arun Siluvery authored
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Arun Siluvery authored
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Arun Siluvery authored
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Arun Siluvery authored
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Arun Siluvery authored
WA in this function should be ordered based on register address. The following order is suggested (Ville), instpm mi_mode row chicken half slice chicken common slice chicken hdc chicken cache_mode_0 cache_mode_1 gt_mode Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Arun Siluvery authored
Dropping it because it is for pre-production stepping, also removed bit definition in i915_reg.h as it is not used anywhere else. Signed-off-by:
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Arun Siluvery authored
Dropping it because it is for pre-production stepping, also removed bit definition in i915_reg as it is not used anywhere else. Signed-off-by:
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Arun Siluvery authored
Dropping it because it is for pre-production stepping. Signed-off-by:
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Arun Siluvery authored
Updated WA with the name. Signed-off-by:
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Arun Siluvery authored
Merge Wa4x4STCOptimizationDisable and WaDisablePartialResolveInVc to save an entry in WA array. Signed-off-by:
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Arun Siluvery authored
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Mika Kahola authored
This patch adds information of current and maximum CD clock frequency and pixel clock frequency information on 'i915_debugfs.c'. v2: - combined seperate patches for current CD clock, maximum CD clock and maximum pixel clock - space added between the frequency value and the unit Signed-off-by:
Mika Kahola <mika.kahola@intel.com> Reviewed-by:
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Ville Syrjälä authored
Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Ville Syrjälä authored
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Ville Syrjälä authored
v2: Deal with _CURABASE too Signed-off-by:
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Ville Syrjälä authored
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Ville Syrjälä authored
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Ville Syrjälä authored
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Ville Syrjälä authored
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Ville Syrjälä authored
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Ville Syrjälä authored
Handle the HDMI aspect ratio property the same way in the SDVO code as we handle it in the HDMI code. v2: Remove stray whitespace change Signed-off-by:
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Ville Syrjälä authored
Make adjusted_mode const whereever we don't have to modify it. This only covers cases when we have a local adjusted_mode variable, and doesn't make any difference for cases where we just dereference pipe_config->adjusted_mode. Signed-off-by:
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Ville Syrjälä authored
We shouldn't frob adjusted_mode after .compute_config(), so move the infoframe aspect ratio setup to .compute_config() from intel_hdmi_set_avi_infoframe(). Signed-off-by:
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Ville Syrjälä authored
The adjustead_mode crtc_ timings are what we will program into the hardware, so it's those timings we should be looking practically everywhere. The normal and crtc_ timings should differ only when stere doubling is used. In that case the normal timings are the orignal non-doubled timigns, and crtc_ timings are the doubled timings used by the hardware. The only case where we continue to look at the normal timings is when we pass the adjusted_mode to drm_match_{cea,hdmi}_mode() to find the VIC. drm_edid keeps the modes aronund in the non-double form only, so it needs the non-double timings to match against. Done with sed 's/adjusted_mode->\([vhVH]\)/adjusted_mode->crtc_\1/g' 's/adjusted_mode->clock/adjusted_mode->crtc_clock/g' with a manual s/VDisplay/vdisplay/ within the comment in intel_dvo.c v2: Update due to intel_dsi.c changes Reviewed-by: -
Ville Syrjälä authored
Rename the function argument to 'adjusted_mode' whenever the function only ever gets passed the adjusted_mode. v2: Update due to intel_dsi.c changes Signed-off-by:
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Paulo Zanoni authored
Make the giant function a little less giant. Signed-off-by:
Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by:
Chris Wilson <chris@chris-wilson.co.uk> [danvet: Add pipe_ prefix as suggested by Chris.] Signed-off-by:
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Paulo Zanoni authored
Make it clear that we're checking whether FBC is supported or not. The fact that the vfunc is not NULL is just a consequence. Another name option would have been fbc_initialized(). Signed-off-by:
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Paulo Zanoni authored
The spec says we just can't use it. v2: - Add WA name (Ville). - Add a big comment explaining that we still didn't fix the problem where we inherit a framebuffer on the first page (Chris, Ville). Signed-off-by: -
Maarten Lankhorst authored
This fixes the warnings like "plane A assertion failure, should be disabled but not" that on the initial modeset during boot. This can happen if the primary plane is enabled by the firmware, but inheriting it fails because the DMAR is active or for other reasons. Most likely caused by commit 36750f28 Author: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Date: Mon Jun 1 12:49:54 2015 +0200 drm/i915: update plane state during init This is the 4.4 version of commit 721a09f7 Author: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Date: Tue Sep 15 14:28:54 2015 +0200 drm/i915: Add primary plane to mask if it's visible Reported-by:
Andreas Reis <andreas.reis@gmail.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91429Reported-and-tested-by:
Emil Renner Berthing <kernel@esmil.dk> Tested-by:
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Ville Syrjälä authored
v2: Hide the 945 vs. rest of gen2/3 difference in the macro Signed-off-by:
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Sonika Jindal authored
Bspec update tells that we have to enable oscaledcompmethod instead of ouniqetrangenmethod for enabling scale value during swing programming. v2: Adding back 'don't care' values to bxt_ddi_translations_dp and add error message if ouniquetrangemethod was set (Imre) Signed-off-by:
Sonika Jindal <sonika.jindal@intel.com> Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>(v1) Reviewed-by:
Imre Deak <imre.deak@intel.com> Signed-off-by:
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Sonika Jindal authored
Adding voltage swing table for edp to support low vswings. v2: Rebased. Signed-off-by:
Sivakumar Thulasimani <sivakumar.thulasimani@intel.com> Signed-off-by:
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Jesse Barnes authored
According to the PCI docs and Rafael, we don't need to be doing explicit enables and disables in our init and teardown routines, as they're taken care of by the PCI core. So drop the pm_runtime_disable() at teardown and pm_runtime_set_active() at init. This fixes one failure of the basic-pci-d3-state test on my BYT. v2: drop extra get_noresume() and put_noidle() (Rafael) Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org> Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net> Acked-by:
"Rafael J. Wysocki" <rjw@rjwysocki.net> Signed-off-by:
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Alex Dai authored
Bit 16 of GuC status indicates resuming from RC6. The LAPIC_DONE status is a reliable readiness flag only when resuming from RC6. This fix a racing issue that allocation of doorbell fails whilst GuC init is not finished. Signed-off-by:
Alex Dai <yu.dai@intel.com> Reviewed-by:
Sagar Arun Kamble <sagar.a.kamble@intel.com> Signed-off-by:
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Ville Syrjälä authored
Always name any variable pointing at the adjusted mode as 'adjustead_mode'. This will make it much easier to identify when we should use the crtc_ timings and when we shoudln't. Conversion was performed with coccinelle: @@ expression E; identifier I; @@ - struct drm_display_mode *I = &E.adjusted_mode; + struct drm_display_mode *adjusted_mode = &E.adjusted_mode; <... - I + adjusted_mode ...> Signed-off-by:
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Ville Syrjälä authored
Replace intel_dvo->panel_fixed_mode with the appropriate intel_panel stuff. Now all connectors that have a fixed mode use intel_panel. Signed-off-by:
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Animesh Manna authored
Another interesting criteria to work dmc as expected is pw1 to be enabled by driver and dmc will shut it off in its execution sequence. If already disabled by driver dmc will get confuse and behave differently than expected found during pc10 entry issue for skl. So berfore we disable power-well 1, added check if dmc firmware is present and driver will not disable power well 1, but for any reason if firmware is not present of failed to load we can shut off the power well 1 which will save some power. As skl is currently fully dependent on dmc to go in lowest possible power state (dc6) but the same is not applicable for bxt. Display engine can enter into dc9 without dmc, hence unblocking disable call. v1: Initial version. v2: Rebased as per current patch series. Cc: Daniel Vetter <daniel.vetter@intel.com> Cc: Damien Lespiau <damien.lespiau@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Sunil Kamath <sunil.kamath@intel.com> Signed-off-by:
Animesh Manna <animesh.manna@intel.com> Signed-off-by:
Vathsala Nagaraju <vathsala.nagaraju@intel.com> Reviewed-by:
A.Sunil Kamath <sunil.kamath@intel.com> Signed-off-by:
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Animesh Manna authored
While display engine entering into low power state no need to disable cdclk pll as CSR firmware of dmc will take care. If pll is already enabled firmware execution sequence will be blocked. This is one of the criteria for dmc to work properly. v1: Initial version. v2: Based on review comment from Daniel added code commnent. Cc: Daniel Vetter <daniel.vetter@intel.com> Cc: Damien Lespiau <damien.lespiau@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Sunil Kamath <sunil.kamath@intel.com> Signed-off-by:
Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Reviewed-by:
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