1. 03 Mar, 2016 19 commits
  2. 02 Mar, 2016 7 commits
    • Stephen Boyd's avatar
      Merge tag 'imx-clk-4.6' of... · 5788923b
      Stephen Boyd authored
      Merge tag 'imx-clk-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-next
      
      Pull i.MX clk updates from Shawn Guo:
      
      The i.MX clock update for 4.6:
      - Add the clock driver support for the latest i.MX6 family SoCs
        addition - i.MX6QP.
      - Clean up the whitespace in i.MX6UL clock driver and add the missing
        KPP clock.
      - Correct pwm7 clock name in i.MX6UL clock driver.
      
      * tag 'imx-clk-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
        clk: imx: add kpp clock for i.MX6UL
        clk: imx: whitespace cleanup; no functional change
        clk: imx: correct pwm7 clock name in driver for i.MX6UL
        clk: imx: Add clock support for imx6qp
      5788923b
    • Stephen Boyd's avatar
      Merge tag 'sunxi-clocks-for-4.6' of... · 06a98527
      Stephen Boyd authored
      Merge tag 'sunxi-clocks-for-4.6' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next
      
      Pull Allwinner clk updates from Maxime Ripard:
      
      Allwinner clocks additions for 4.6
      
      A bunch of things, mostly:
        - Finally switched everything over to OF_CLK_DECLARE, which should remove
          orphans clocks entirely
        - Reworked the clk-factors to be able to add new parameters
        - Improved the error reporting
        - A bunch of new clocks for new SoCs.
      
      * tag 'sunxi-clocks-for-4.6' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: (25 commits)
        clk: sunxi: Add apb0 gates for H3
        clk: sunxi: Improve divs_clk error handling and reporting
        clk: sunxi: improve divider_clk error handling and reporting
        clk: sunxi: improve mux_clk error handling and reporting
        clk: sunxi: Fix sun8i-a23-apb0-clk divider flags
        clk: sunxi: Remove clk_register_clkdev calls
        clk: sunxi: Remove old probe and protection code
        clk: sunxi: convert current clocks registration to CLK_OF_DECLARE
        clk: sunxi: Make clocks setup functions take const pointer
        clk: sunxi: Make clocks setup functions return their clock
        clk: sunxi: improve error reporting for the mux clock
        clk: sunxi: don't mark sun6i_ar100_data __initconst
        clk: sunxi: add bus gates for A83T
        clk: sunxi: Add apb0 gates for A83T
        clk: sunxi: rewrite sun8i-a23-mbus-clk using the simpler composite clk
        clk: sunxi: rewrite sun6i-ar100 using factors clk
        clk: sunxi: rewrite sun6i-a31-ahb1-clk using factors clk with custom recalc
        clk: sunxi: factors: Drop round_rate from clk ops
        clk: sunxi: factors: Support custom formulas
        clk: sunxi: factors: Consolidate get_factors parameters into a struct
        ...
      06a98527
    • Stephen Boyd's avatar
      clk: qcom: msm8960: Fix ce3_src register offset · 0f75e1a3
      Stephen Boyd authored
      The offset seems to have been copied from the sata clk. Fix it so
      that enabling the crypto engine source clk works.
      Tested-by: default avatarSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
      Tested-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
      Fixes: 5f775498 ("clk: qcom: Fully support apq8064 global clock control")
      Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      0f75e1a3
    • Michael Turquette's avatar
      Merge branch 'clk-ti' into clk-next · 3b0f4ae3
      Michael Turquette authored
      Conflicts:
      	drivers/clk/Kconfig
      3b0f4ae3
    • Stephen Boyd's avatar
      clk: ti: Fix some errors found by static checkers · 8a8b6eb7
      Stephen Boyd authored
      drivers/clk/ti/clk-814x.c:34:12: warning: symbol 'dm814x_adpll_early_init' was not declared. Should it be static?
      drivers/clk/ti/clk-814x.c:58:12: warning: symbol 'dm814x_adpll_enable_init_clocks' was not declared. Should it be static?
      drivers/clk/ti/adpll.c:465 ti_adpll_recalc_rate() warn: should '__readw(d->regs + 20) << 18' be a 64 bit type?
      drivers/clk/ti/adpll.c:945 ti_adpll_probe() error: we previously assumed 'd->clocks' could be null (see line 921)
      
      The last one looks like a real bug because we don't return an
      error on allocation failure.
      
      Cc: Tero Kristo <t-kristo@ti.com>
      Tested-by: default avatarTony Lindgren <tony@atomide.com>
      Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      8a8b6eb7
    • Tony Lindgren's avatar
      clk: ti: Allow COMPILE_TEST to build selected drivers · c2ee9bdc
      Tony Lindgren authored
      The arch independent drivers can be build testeed with
      COMPILE_TEST. Let's allow that for drivers/clk/ti.
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      Signed-off-by: default avatarMichael Turquette <mturquette@baylibre.com>
      c2ee9bdc
    • Tony Lindgren's avatar
      clk: ti: Add support for dm814x ADPLL · 21330497
      Tony Lindgren authored
      On dm814x we have 13 ADPLLs with 3 to 4 outputs on each. The
      ADPLLs have several dividers and muxes controlled by a shared
      control register for each PLL.
      
      Note that for the clocks to work as device drivers for booting on
      dm814x, this patch depends on "ARM: OMAP2+: Change core_initcall
      levels to postcore_initcall" that has already been merged.
      
      Also note that this patch does not implement clk_set_rate for the
      PLL, that will be posted later on when available.
      
      Cc: Stephen Boyd <sboyd@codeaurora.org>
      Acked-by: default avatarTero Kristo <t-kristo@ti.com>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      Signed-off-by: default avatarMichael Turquette <mturquette@baylibre.com>
      21330497
  3. 29 Feb, 2016 1 commit
    • Archit Taneja's avatar
      clk: qcom: Fix pre-divider usage for pixel RCG · 811a498e
      Archit Taneja authored
      The clk_rcg_pixel_set_rate clk_op sets up the pre-divider by reading
      its current value from the NS register.
      
      Using the pre-divider wasn't really intended when creating these ops.
      The pixel RCG was only intended to achieve fractional multiplication
      provided in the pixel_table array. Leaving the pre-divider to the
      existing register value results in a wrong pixel clock when the
      bootloader sets up the display. This was left unidentified because
      the IFC6410 Plus board on which this was verified didn't have a
      bootloader that configured the display.
      
      Don't set the RCG pre-divider in freq_tbl to the existing NS register
      value. Force it to 1 and only use the M/N counter to achieve the desired
      fractional multiplication.
      
      Cc: Vinay Simha <vinaysimha@inforcecomputing.com>
      Signed-off-by: default avatarArchit Taneja <architt@codeaurora.org>
      Tested-by: default avatarJohn Stultz <john.stultz@linaro.org>
      Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      811a498e
  4. 28 Feb, 2016 2 commits
  5. 27 Feb, 2016 10 commits
  6. 26 Feb, 2016 1 commit