- 26 Sep, 2017 40 commits
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Sylvia Tsai authored
They could differ between ASIC generations Signed-off-by:
Sylvia Tsai <sylvia.tsai@amd.com> Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Acked-by:
Tony Cheng <Tony.Cheng@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Charlene Liu authored
Signed-off-by:
Charlene Liu <charlene.liu@amd.com> Acked-by:
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Jordan Lazare authored
Signed-off-by:
Jordan Lazare <Jordan.Lazare@amd.com> Reviewed-by:
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Ding Wang authored
- Set stream signal type to be SST when setting non-tile timing on MST tiled display. - Disable MST on sink after disabling MST link. - Enable MST on sink before enabling MST link. Signed-off-by:
Ding Wang <Ding.Wang@amd.com> Acked-by:
Jun Lei <Jun.Lei@amd.com> Signed-off-by:
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Leon Elazar authored
In MST case during removal of remote sink its descriptor pointer wasn't freed corectly. Signed-off-by:
Leon Elazar <leon.elazar@amd.com> Acked-by:
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Yongqiang Sun authored
Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
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Yongqiang Sun authored
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Sylvia Tsai authored
- Adding dm controlled signal type in dc_stream - Adding fallback to dvi signal when output signal is hdmi and the connector type is not Signed-off-by:
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Leon Elazar authored
1. get_ss_info_from_atombios function was allocating the memory populating the provided pointer but them freeing the memory. Since the pointer was return as a valid value, we are trying to free the same memory during clock resource destruction Signed-off-by:
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Zeyu Fan authored
- Remove x,y hotspot from dc_cursor_attributes. Only program it through setPosition. Signed-off-by:
Zeyu Fan <Zeyu.Fan@amd.com> Acked-by:
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Charlene Liu authored
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Mario Kleiner authored
Make sure we do not program a hw pageflip inside vblank 'n' iff the atomic flip is comitted while inside the same vblank 'n'. We must defer such a flip by one refresh cycle to vblank 'n+1', unless this is a DRM_MODE_PAGE_FLIP_ASYNC async pageflip, which must always execute as soon as possible. Without this, pageflips programmed via X11 GLX_OML_sync_control extensions glXSwapBuffersMscOML(..., target_msc, ...); call and/or via DRI3/Present PresentPixmap(..., target_msc, ...); request will complete one vblank too early whenever target_msc > current_msc + 1, ie. more than 1 vblank in the future. In such a case, the call of the pageflip ioctl() would be triggered by a queued drmWaitVblank() vblank event, which itself gets dispatched inside the vblank one frame before the target_msc vblank. Testing with this patch does no longer show any problems with OML_sync_control swap scheduling or flip completion timestamps. Tested on R9 380 Tonga. v2: Add acked/r-b by Harry and Michel. v3: Feedback from Andrey: Must not wait an extra frame for DRM_MODE_PAGE_FLIP_ASYNC flips. Signed-off-by:Mario Kleiner <mario.kleiner.de@gmail.com> Acked-by: Harry Wentland <harry.wentland@amd.com> (v1) Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com> Reviewed-by:
Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Cc: Harry Wentland <Harry.Wentland@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
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Mario Kleiner authored
Since DC now uses CRTC_VERTICAL_INTERRUPT0 as VBLANK irq trigger and vblank interrupts actually happen earliest at start of vblank, instead of a bit before vblank, we no longer need some of the fudging logic to deal with too early vblank irq handling (grep for lb_vblank_lead_lines). This itself fixes a pageflip scheduling bug in DC, caused by uninitialized use of lb_vblank_lead_lines, with a wrong startup value of 0. Thanks to the new vblank irq trigger this value of zero is now actually correct for DC :). A new problem is that vblank irq's race against pflip irq's, and as both can fire at first line of vblank, it is no longer guaranteed that vblank irq handling (therefore -> drm_handle_vblank() -> drm_update_vblank_count()) executes before pflip irq handling for a given vblank interval when a pageflip completes. Therefore the vblank count and timestamps emitted to user-space as part of the pageflip completion event will be often stale and cause new timestamping and swap scheduling errors in user-space. This was observed with large frequency on R9 380 Tonga Pro. Fix this by enforcing a vblank count+timestamp update right before emitting the pageflip completion event from the pflip irq handler. The logic in core drm_update_vblank_count() makes sure that no redundant or conflicting updates happen, iow. the call turns into a no-op if it wasn't needed for that vblank, burning a few microseconds of cpu time though. Successfully tested on AMD R9 380 "Tonga Pro" (VI/DCE 10) with DC enabled on the current DC staging branch. Independent measurement of pageflip completion timing with special hardware measurement equipment now confirms correct pageflip timestamps and counts in the pageflip completion events. v2: Review comments by Michel, drop outdated paragraph about problem already fixed in 2nd patch of the series. Add acked/r-b by Harry and Michel. Signed-off-by: -
Pratik Vishwakarma authored
DRM_IOCTL_MODE_GETCONNECTOR fails with EINVAL on enabling DRIVER_ATOMIC With this DRM_IOCTL_MODE_GETCONNECTOR returns all the connector properties. freesync_property and freesync_capable_property return 0 currently. TESTS(On Chromium OS on Stoney Only) * Builds without compilation errors. * 'atomictest' proceeds after applying patch and fails with vblank event timed out. * Chromium OS ui comes up. Signed-off-by:
Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Reviewed-by:
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Harry Wentland authored
We still rely on legacy properties. Fallback on legacy properties until we get to pull these into some atomic state. Signed-off-by:
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Harry Wentland authored
4.9 kernel will always add the assigned crtc to possible_crtcs on a plane. This is no longer the case on newer kernels. Make sure we allow any plane on any crtc. Signed-off-by:
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Alex Deucher authored
Signed-off-by:
Roman Li <Roman.Li@amd.com> Signed-off-by:
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Andrey Grodzovsky authored
Avoid enabling CRTC_VERTICAL_INTERRUPT0 twice on resume. It's enabled once from within manage_dm_interrupts in mode set and another explicitly from amdgpu_dm_irq_resume_late. Seems it lead to CRTC hang. Signed-off-by:
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Jordan Lazare authored
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Yongqiang Sun authored
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Jordan Lazare authored
PPLib is now calling into DC to get vrefresh and min_vblank_time, but since full bandwidth calcs are missing for those generations, the pplib structures were never being filled. This change fills the currently required fields to prevent screen corruption. Signed-off-by:
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Amy Zhang authored
- Correct the aux channel selection according to DAL3 Signed-off-by:
Amy Zhang <Amy.Zhang@amd.com> Acked-by:
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Andrey Grodzovsky authored
Allow Linux to use DRM provided EDID read functioality by moving DAL edid implementation to module hence removing this code from DC by this cleaning up DC code for upstream. v2: Removing ddc_service. No more need for it. Signed-off-by:
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Andrey Grodzovsky authored
I2C_M_RD was translated to write instead of read. Signed-off-by:
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Andrey Grodzovsky authored
Keep 1:1 relation between MST sink and it's MST connector. Signed-off-by:
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Andrey Grodzovsky authored
We can keep a 1:1 relation between a link and a physical connector and hence skip the iteration. This function is used in context of only physical connetors. Signed-off-by:
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Dmytro Laktyushkin authored
Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Zeyu Fan authored
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Reza Amini authored
Signed-off-by:
Reza Amini <reza.amini@amd.com> Reviewed-by:
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Reza Amini authored
Surface information is by default copied from old context in dc_commit_stream. Thus unchange streams will not be affected. For new streams, we shouldn't validate the new mode against the surface configuration of old_context. Signed-off-by:
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Shirish S authored
This patch introduces amdgpu_drm_plane_state structure, which subclasses drm_plane_state and holds data suitable for configuring hardware. It switches reset(), atomic_duplicate_state() & atomic_destroy_state() functions to new internal implementation, earlier they were pointing to drm core functions. TESTS(On Chromium OS on Stoney Only) * Builds without compilation errors. * 'plane_test' passes for XR24 format based Overlay plane. * Chromium OS ui comes up. Signed-off-by:
Shirish S <shirish.s@amd.com> Signed-off-by:
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Harry Wentland authored
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Alex Deucher authored
Current design has per-crtc-plane model. As a result, for asic's that support underlay, are unable to expose it to user space for modesetting. To enable this, the drm driver intialisation now runs for number of surfaces instead of stream/crtc. This patch plumbs surface capabilities to drm framework so that it can be effectively used by user space. Tests: (On Chromium OS for Stoney Only) * 'modetest -p' now shows additional plane with YUV capabilities in case of CZ and ST. * 'plane_test' fails with below error: [drm:amdgpu_dm_connector_atomic_set_property [amdgpu]] *ERROR* Unsupported screen depth 0 as ther is no support for YUYV * Checked multimonitor display works fine Signed-off-by:
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Ding Wang authored
ASICs using bios parser 1 don't check HBR3 capability as there is no such a bit usHBR3En in ATOM_ENCODER_CAP_RECORDER. Therefore, will use ATOM_ENCODER_CAP_RECORDER_V2 and thus obtain the usHBR3En bit. Signed-off-by:
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Vitaly Prosyak authored
Frame sequential, top-bottom and side-by-side support. Signed-off-by:
Vitaly Prosyak <vitaly.prosyak@amd.com> Acked-by:
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Tony Cheng authored
Signed-off-by:
Hersen Wu <hersenxs.wu@amd.com> Signed-off-by:
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Yongqiang Sun authored
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Roman Li authored
In some use-cases, e.g. multiple 4K displays, exisitng wait time for reg update of 30msec timed out during mode setiing that sometimes resulted in system bad state as we continue without waiting for registry update complete. Increasing timeout to 35msec fixes that problem. Signed-off-by:
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Charlene Liu authored
Signed-off-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Signed-off-by:
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Andrey Grodzovsky authored
Register ISR hnadler on the new interrupt. Signed-off-by:
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