- 18 Jul, 2019 33 commits
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Xiaojie Yuan authored
Same as navi10. v2: squash in logic fix (Colin Ian King) v3: squash in logic simplification (Alex) Signed-off-by:
Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by:
Snow Zhang <Snow.Zhang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Xiaojie Yuan authored
Virtual display is a sw based kms interface for virtualization and emulation. Signed-off-by:
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Xiaojie Yuan authored
Add the initial IP blocks for navi14 Signed-off-by:
Jack Xiao <Jack.Xiao@amd.com> Signed-off-by:
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Xiaojie Yuan authored
same as navi10 Signed-off-by:
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Jack Xiao authored
max fifo size is 128 and PA_SC_FIFO_SIZE[20:15]=SC_HIZ_TILE_FIFO_SIZE field is programmed in units of two entries, but 6 bits is insufficient to hold value 128/2 = 64, so set this field as 0 which is interpreted by the hardware as maximum physical fifo size(128). Signed-off-by:
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Tao Zhou authored
Updated settings from hw team. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Acked-by:
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Xiaojie Yuan authored
Add updated settings from hw team. Signed-off-by:
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Xiaojie Yuan authored
Updated settings for hw team. Signed-off-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
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Xiaojie Yuan authored
Add golden settings for navi14. Signed-off-by:
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Xiaojie Yuan authored
Needed for clockgating. Signed-off-by:
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Xiaojie Yuan authored
Update settings for navi14. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Xiaojie Yuan authored
Same as navi10. Signed-off-by:
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Xiaojie Yuan authored
Add navi14 to appropriate cases. Signed-off-by:
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Xiaojie Yuan authored
Same as navi10. Signed-off-by:
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Xiaojie Yuan authored
Add gfx config details for navi14. Signed-off-by:
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Xiaojie Yuan authored
To be filled in once available. Signed-off-by:
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Xiaojie Yuan authored
Add support for navi14 CP firmware files. Signed-off-by:
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Xiaojie Yuan authored
same as navi10. Signed-off-by:
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tiancyin authored
add new registers: mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL Reviewed-by:
tiancyin <tianci.yin@amd.com> Signed-off-by:
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Xiaojie Yuan authored
Add settings for navi14. Signed-off-by:
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Xiaojie Yuan authored
To be filled in once they are available. Signed-off-by:
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Xiaojie Yuan authored
Add support for navi14 sdma firmware files. Signed-off-by:
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Xiaojie Yuan authored
same as navi10 Signed-off-by:
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Xiaojie Yuan authored
max instance number is 6 for navi10 and 7 for navi14, and we increase the reg_offset array size to avoid out-of-bound access Signed-off-by:
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Xiaojie Yuan authored
Add IP discovery for navi14. Signed-off-by:
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Xiaojie Yuan authored
Initialize the IP register base offsets for navi14. v2: squash in MP, CLK, THM updates Signed-off-by:
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Xiaojie Yuan authored
Same as navi10. Signed-off-by:
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Xiaojie Yuan authored
same with navi10 Signed-off-by:
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Xiaojie Yuan authored
Add navi14 to case statement to load the GPU info firmware. Signed-off-by:
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Xiaojie Yuan authored
Add CHIP_NAVI14 to the list of asic types. Signed-off-by:
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hersen wu authored
[WHY] dc sw clock implementation of navi10 and raven are not exact the same. dcccg, dchub reference clock initialization is done after dc calls vbios dispcontroller_init table. for raven family, before dispcontroller_init is called by dc, the ref clk values are referred by sw clock implementation and program asic register using wrong values. this causes dchub pstate error. This need provide valid ref clk values. for navi10, since dispcontroller_init is not called, dchubbub_global_timer_enable = 0, hubbub2_get_dchub_ref_freq will hit aeert. this need remove hubbub2_get_dchub_ref_freq from this location and move to dcn20_init_hw. [HOW] for all asic, initialize dccg, dchub ref clk with data from vbios firmware table by default. for raven asic family, use these data from vbios, for asic which support sw dccg component, like navi10, read ref clk by sw dccg functions and update the ref clk. Signed-off-by:
hersen wu <hersenxs.wu@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
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Alex Deucher authored
The dpm sensor function already does this for us. This fixes the freq*_input files with the new SMU implementation. Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Nicholas Kazlauskas authored
Workaround for now to avoid underflow. The uclk switch time should really be bumped up to 404, but doing so would expose p-state hang issues for higher bandwidth display configurations. Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
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- 17 Jul, 2019 7 commits
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Joseph Greathouse authored
If we shut down a process without having destroyed its GWS-using queues, it is possible that GWS BO will still be in the process BO list during the gpuvm destruction. This list should be empty at that time, so we should remove the GWS allocation at the process uninit point if it is still around. Signed-off-by:
Joseph Greathouse <Joseph.Greathouse@amd.com> Acked-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Tom St Denis authored
The register debugfs interface was using the wrong bitmask for vmid selection for GFX_CNTL. Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
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Evan Quan authored
Optimization for the socket power calculation is introduced. Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Signed-off-by:
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Evan Quan authored
Do not halt driver loading on if_version mismatch. As our driver and FWs are backward compatible. Signed-off-by:
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Evan Quan authored
The interface was used in a confusing way. In profile mode scenario, the 2nd parameter of the interface was used in a different way from other scenarios. Signed-off-by:
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Evan Quan authored
As the lock was already held on the entrance to smu_handle_task. - V2: lock in small granularity Signed-off-by:
Kevin Wang <kevin1.wang@amd.com> Signed-off-by:
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Evan Quan authored
No access before allocation. Signed-off-by:
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