- 18 Jan, 2022 18 commits
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Aric Cyr authored
This version brings improvements in the following: - Drop unnecessary DCN guards - Improve Z9 interface Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Eric Yang authored
[Why] Need to disable Z9 on configurations that only support Z10 [How] Support new PMFW interface to disable Z9 Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Eric Yang <Eric.Yang2@amd.com> Tested-by:
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Eric Yang authored
Might potentially have truncation problem with the implicit casting Reviewed-by:
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Jarif Aftab authored
[WHY] - We only ever want seamless boots on eDPs - The naming and logic did not match the context [HOW] - Removed unnecessary if statements - Renamed power_down_display_on_boot to seamless_boot_edp_requested and swapped the logic Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Acked-by:
Jarif Aftab <jaraftab@amd.com> Tested-by:
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Christian König authored
The return value was never initialized so the cleanup code executed when it isn't even necessary. Just add proper error handling. Fixes: ab50cb9d ("drm/radeon/radeon_kms: Fix a NULL pointer dereference in radeon_driver_open_kms()") Signed-off-by:
Christian König <christian.koenig@amd.com> Tested-by:
Jan Stancek <jstancek@redhat.com> Tested-by:
Borislav Petkov <bp@suse.de> Reviewed-by:
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Marina Nikolic authored
Enable power level, power limit and fan speed information retrieval in one VF mode. This is required so that tool ROCM-SMI can provide this information to users. Signed-off-by:
Marina Nikolic <Marina.Nikolic@amd.com> Acked-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Kevin Wang <kevinyang.wang@amd.com> Signed-off-by:
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Jingwen Chen authored
[Why] This fixes 892deb48 ("drm/amdgpu: Separate vf2pf work item init from virt data exchange"). we should read pf2vf data based at mman.fw_vram_usage_va after gmc sw_init. commit 892deb48 breaks this logic. [How] calling amdgpu_virt_exchange_data in amdgpu_virt_init_data_exchange to set the right base in the right sequence. v2: call amdgpu_virt_init_data_exchange after gmc sw_init to make data exchange workqueue run v3: clean up the code logic v4: add some comment and make the code more readable Fixes: 892deb48 ("drm/amdgpu: Separate vf2pf work item init from virt data exchange") Signed-off-by:
Jingwen Chen <Jingwen.Chen2@amd.com> Reviewed-by:
Horace Chen <horace.chen@amd.com> Signed-off-by:
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yipechai authored
drm/amdgpu: Fix the code style warnings in hdp xgmi mca and umc: 1. WARNING: missing space after struct definition. 2. WARNING: please, no space before tabs. 3. WARNING: line length of xxx exceeds 100 columns. 4. ERROR: "foo* bar" should be "foo *bar". 5. ERROR: space required before the open parenthesis '('. 6. ERROR: space prohibited after that open parenthesis '('. Signed-off-by:yipechai <YiPeng.Chai@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Acked-by:
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yipechai authored
Fix the code style warnings in sdma: 1. WARNING: Missing a blank line after declarations. 2. ERROR: that open brace { should be on the previous line. 3. WARNING: unnecessary whitespace before a quoted newline. 4. ERROR: space required after that ',' (ctx:VxV). Signed-off-by: -
yipechai authored
Fix the code style warnings in gmc: ERROR: space required after that ',' (ctx:VxV). Signed-off-by:
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yipechai authored
Fix the code style warnings in gfx: 1. WARNING: suspect code indent for conditional statements. 2. ERROR: spaces required around that '=' (ctx:WxV). Signed-off-by:
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yipechai authored
Fix the code style warnings in amdgpu_ras: 1. ERROR: space required before the open parenthesis '('. 2. WARNING: line length of xxx exceeds 100 columns. 3. ERROR: "foo* bar" should be "foo *bar". 4. WARNING: unnecessary whitespace before a quoted newline. 5. WARNING: space prohibited before semicolon. 6. WARNING: suspect code indent for conditional statements. 7. WARNING: braces {} are not necessary for single statement blocks. Signed-off-by: -
Guchun Chen authored
This is a following patch to apply the workaround only on those boards with a bad harvest table in ip discovery. Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
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Guchun Chen authored
Early check in amdgpu_discovery_reg_base_init promises this. Signed-off-by:
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Stanley.Yang authored
Changed from v1: remove unused brace Signed-off-by:Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by:
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mziya authored
support ECC TABLE message, this table include umc ras error count and error address V2: Return after smu version check fail V3: Return -EOPNOTSUPP, if fail to get smc ver. V4: ECCTABLE typo corrected and sentence rephrased. Signed-off-by:
mziya <Mohammadzafar.ziya@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
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mziya authored
add smu message query error information interface, function name align with IP version number V2: Removed unused err cnt entry Signed-off-by:
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mziya authored
update smu driver if version to 0x40 V2: Interface version append with sienna_cichlid V3: Aligned with latest driver interface. Reviewed-by:
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- 14 Jan, 2022 22 commits
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Mario Limonciello authored
The WA from commit 2a50edbf ("drm/amd/display: Apply w/a for hard hang on HPD") and commit 1bd3bc74 ("drm/amd/display: Extend w/a for hard hang on HPD to dcn20") causes a regression in s0ix where the system will fail to resume properly on many laptops. Pull the workarounds out to avoid that s0ix regression in the common case. This HPD hang happens with an external device in special circumstances and a new W/A will need to be developed for this in the future. Cc: Qingqing Zhuo <qingqing.zhuo@amd.com> Reported-by:
Scott Bruce <smbruce@gmail.com> Reported-by:
Chris Hixon <linux-kernel-bugs@hixontech.com> Reported-by: spasswolf@web.de Link: https://bugzilla.kernel.org/show_bug.cgi?id=215436 Link: https://gitlab.freedesktop.org/drm/amd/-/issues/1821 Link: https://gitlab.freedesktop.org/drm/amd/-/issues/1852 Fixes: 2a50edbf ("drm/amd/display: Apply w/a for hard hang on HPD") Fixes: 1bd3bc74 ("drm/amd/display: Extend w/a for hard hang on HPD to dcn20") Reviewed-by:
Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:
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Alex Deucher authored
Support for IP based discovery is in place now so this check is no longer required. Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Lukas Fink authored
eb4fd29a ("drm/amdgpu: bind to any 0x1002 PCI diplay class device") added generic bindings to amdgpu so that that it binds to all display class devices with VID 0x1002 and then rejects those in amdgpu_pci_probe. Unfortunately it reuses a driver_data value of 0 to detect those new bindings, which is already used to denote CHIP_TAHITI ASICs. The driver_data value given to those new bindings was changed in dd0761fd24ea1 ("drm/amdgpu: set CHIP_IP_DISCOVERY as the asic type by default") to CHIP_IP_DISCOVERY (=36), but it seems that the check in amdgpu_pci_probe was forgotten to be changed. Therefore, it still rejects Tahiti GPUs. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/1860 Fixes: eb4fd29a ("drm/amdgpu: bind to any 0x1002 PCI diplay class device") Signed-off-by:
Lukas Fink <lukas.fink1@gmail.com> Signed-off-by:
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Alex Deucher authored
It can cause a hang. This is normally not enabled for GPU hangs on these asics, but was recently enabled for handling aborted suspends. This causes hangs on some platforms on suspend. Fixes: daf8de08 ("drm/amdgpu: always reset the asic in suspend (v2)") Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1858Signed-off-by:
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Alex Deucher authored
Rather than opting into GPU recovery support, default to on, and opt out if it's not working on a particular GPU. This avoids the need to add new asics to this list since this is a core feature. Reviewed-by:
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CHANDAN VURDIGERE NATARAJ authored
Add yellow carp to devices which support recovery Signed-off-by:
CHANDAN VURDIGERE NATARAJ <chandan.vurdigerenataraj@amd.com> Reviewed-by:
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Jiapeng Chong authored
dpg_width is being initialized to width but this is never read as dpg_width is overwritten later on. Remove the redundant initialization. Cleans up the following clang-analyzer warning: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dp.c:6020:8: warning: Value stored to 'dpg_width' during its initialization is never read [clang-analyzer-deadcode.DeadStores]. Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Signed-off-by:
Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by:
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Changcheng Deng authored
There is a regular need in the kernel to provide a way to declare having a dynamically sized set of trailing elements in a structure. Kernel code should always use "flexible array members" for these cases. The older style of one-element or zero-length arrays should no longer be used. Reference: https://www.kernel.org/doc/html/latest/process/deprecated.html#zero-length-and-one-element-arraysReported-by:
Zeal Robot <zealci@zte.com.cn> Signed-off-by:
Changcheng Deng <deng.changcheng@zte.com.cn> Signed-off-by:
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Flora Cui authored
check null ptr first before access its element v2: check adev->pm.dpm_enabled early in amdgpu_debugfs_pm_init() Signed-off-by:
Flora Cui <flora.cui@amd.com> Reviewed-by:
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yipechai authored
fix compile warning for ras_block_match_default Signed-off-by:
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yipechai authored
Use ARRAY_SIZE to get array length. Signed-off-by:
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Yang Li authored
Eliminate the follow smatch warnings: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:3504 amdgpu_device_init() warn: inconsistent indenting drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:1716 amdgpu_ras_error_status_query() warn: if statement not indented drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:1058 amdgpu_ras_error_inject() warn: inconsistent indenting Reported-by:
Yang Li <yang.lee@linux.alibaba.com> Signed-off-by:
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Yang Li authored
Eliminate the following coccicheck warning: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:2725:16-17: Unneeded semicolon Reported-by:
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yipechai authored
No longer insert ras blocks into ras_list if it already exists in ras_list. Signed-off-by:
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yipechai authored
Add ras supported check for register_ras_block. Signed-off-by:
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Bokun Zhang authored
- Add interface to load SRIOV cap FW. If the FW does not exist, simply skip this FW loading routine. This FW will only be loaded under SRIOV. Other driver configuration will not be affected. By adding this interface, it will make us easier to prepare SRIOV Linux guest driver for different users. - Update sysfs interface to read cap FW version. - Refactor PSP FW loading routine under SRIOV to use a unified SWITCH statement instead of using IF statement - Remove redundant amdgpu_sriov_vf() check in FW loading routine Acked-by:
Monk Liu <monk.liu@amd.com> Acked-by:
Bokun Zhang <Bokun.Zhang@amd.com> Signed-off-by:
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Graham Sider authored
Cases should be same indentation as switch. Also fix string spanning across multiple lines. Signed-off-by:
Graham Sider <Graham.Sider@amd.com> Reviewed-by:
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Jonathan Kim authored
Some suggested cleanups to declutter ttm when doing debug VRAM access over SDMA. Signed-off-by:
Jonathan Kim <jonathan.kim@amd.com> Reviewed-by:
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Jonathan Kim authored
For better performance during VRAM access for debugged processes, do read/write copies over SDMA. In order to fulfill post mortem debugging on a broken device, fallback to stable MMIO access when gpu recovery is disabled or when job submission time outs are set to max. Failed SDMA access should automatically fall back to MMIO access. Use a pre-allocated GTT bounce buffer pre-mapped into GART to avoid page-table updates and TLB flushes on access. Signed-off-by:
Felix Kuehling <felix.kuehling@amd.com> Signed-off-by:
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yipechai authored
Removed redundant ras code. Signed-off-by:
John Clements <john.clements@amd.com> Reviewed-by:
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yipechai authored
1. Move xgmi special error inject function from amdgpu_ras.c to xgmi block. 2. Support to use psp_ras_trigger_error as default error inject function in amdgpu_ras.c. If .ras_error_inject isn't defined in ras block, default error inject function will take effect. v2: squash in warning fix (Alex) Signed-off-by:
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yipechai authored
1.Modify mca block to fit for the unified ras block data and ops. 2.Define special .ras_block_match function for mca block to identify itself. 3.Change amdgpu_mca_ras_funcs to amdgpu_mca_ras_block(amdgpu_mca_ras had been used), and the corresponding variable name remove _funcs suffix. 4.Remove the const flag of cma ras variable so that cma ras block can be able to be inserted into amdgpu device ras block link list. 5.Invoke amdgpu_ras_register_ras_block function to register cma ras block into amdgpu device ras block link list. 6.Remove the redundant code about cma in amdgpu_ras.c after using the unified ras block. Signed-off-by:
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