- 12 Feb, 2016 1 commit
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Tom St Denis authored
Replaces switch statements with direct assignments to reduce line count significantly. Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com>
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- 10 Feb, 2016 39 commits
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Rex Zhu authored
In case CONFIG_DRM_AMD_POWERPLAY is defined and amdgpu.powerplay=0. some functions in powrplay can also be called by DAL. and the input parameter is *adev. if just check point not NULL was not enough and will lead to NULL point error. Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Reviewed-by:
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Eric Yang authored
Signed-off-by:
Eric Yang <eric.yang2@amd.com> Reviewed-by:
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Eric Yang authored
Signed-off-by:
Eagle Yeh <eagle.yeh@amd.com> Signed-off-by:
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Rex Zhu authored
Signed-off-by:
Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by:
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Vitaly Prosyak authored
Use min required system clock calculated by dal Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Reviewed-by:
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David Rokhvarg authored
Signed-off-by:
David Rokhvarg <David.Rokhvarg@amd.com> Reviewed-by:
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Rex Zhu authored
Reviewed-by:
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Rex Zhu authored
Reviewed-by:
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Rex Zhu authored
amd_pp_dal_clock_info to amd_pp_simple_clock_info. Signed-off-by:
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Harry Wentland authored
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Vitaly Prosyak authored
Prior actual MMIO flip we need to acquire DAL mutex to guard our target state which get modified on reset mode. Assign page flip status before actual flip to handle the possible race condition with interrupt. Signed-off-by:
Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by:
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Harry Wentland authored
Signed-off-by:
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Christian König authored
No need to keep that for every IB. Signed-off-by:
Christian König <christian.koenig@amd.com> Acked-by:
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Christian König authored
We need the IB test for GPU resets as well and the scheduler should be stoped then. Signed-off-by:
Alex Deucher <alexander.deucer@amd.com> Signed-off-by:
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Christian König authored
We need the IB test for GPU resets as well and the scheduler should be stoped then. Signed-off-by:
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Christian König authored
That's probably a better matching name. Signed-off-by:
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Christian König authored
Add a job_alloc_with_ib helper and proper job submission. Signed-off-by:
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Christian König authored
There is no point in sending them through the scheduler. Signed-off-by:
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Christian König authored
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Christian König authored
We can't submit to multiple rings at the same time anyway. Signed-off-by:
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Christian König authored
The padding depends on the firmware version and we need that for BO moves as well, not only for VM updates. v2: new approach of making pad_ib a ring function v3: fix typo in macro name Signed-off-by:
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Christian König authored
Don't keep that around twice. Signed-off-by:
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Christian König authored
And use them in the CS instead of allocating IBs and jobs separately. Signed-off-by:
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Christian König authored
Specifying no IBs on command submission is invalid, stop crashing badly when somebody tries it. Signed-off-by:
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Christian König authored
Just a leftover from semaphores. Signed-off-by:
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Christian König authored
Just leftovers from the semaphores. Signed-off-by:
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Christian König authored
Instead of when we try to bind it check the usermm when we try to use it in the IOCTLs. Signed-off-by:
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Matthew Dawson authored
When the radeon driver resets a gpu, it attempts to test whether all the rings can successfully handle an IB. If these rings fail to respond, the process will wait forever. Another gpu reset can't happen at this point, as the current reset holds a lock required to do so. Instead, make all the IB tests run with a timeout, so the system can attempt to recover in this case. While this doesn't fix the underlying issue with card resets failing, it gives the system a higher chance of recovering. These timeouts have been confirmed to help both a Tathi and Hawaii card recover after a gpu reset. This also adds a new function, radeon_fence_wait_timeout, that behaves like fence_wait_timeout. It is used instead of fence_wait_timeout as it continues to work during a reset. radeon_fence_wait is changed to be implemented using this function. V2: - Changed the timeout to 1s, as the default 10s from radeon_wait_timeout was too long. A timeout of 100ms was tested and found to be too short. - Changed radeon_fence_wait_timeout to behave more like fence_wait_timeout. Reviewed-by:
Matthew Dawson <matthew@mjdsystems.ca> Signed-off-by:
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Alex Deucher authored
Drop needless function wrapper. Signed-off-by: -
Christian König authored
Move that out of the main IOCTL function. Signed-off-by:
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Christian König authored
And use it in UVD/VCE command patching. v2: squash in Christian's fix Signed-off-by:
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Christian König authored
We only need a few dw here. Signed-off-by:
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Alex Deucher authored
VBIOS does this for us in asic_init. v2: update iceland as well Reviewed-by:
Monk Liu <monk.liu@amd.com> Reviewed-by:
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Alex Deucher authored
VBIOS does this for us in asic_init. Reviewed-by:
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Alex Deucher authored
Generally a good idea between VM sessions. We need a way to detect VM pass-through in general and always run asic_init in that case. Reviewed-by:
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Alex Deucher authored
Required to make desicions about certain code pathes. Reviewed-by:
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Alex Deucher authored
This table is found on boards that support SR-IOV. This will be used to determine if the board supports SR-IOV and allow the driver to take specific action in certain cases. Reviewed-by:
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Alex Deucher authored
amdgpu_boot_test_post_card() is not used anywhere. Probably a leftover from the original port from radeon. Reviewed-by:
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Maruthi Srinivas Bayyavarapu authored
ACP IP have internal DMA controller, DW I2S controller and DSPs as separate power tiles. DMA and I2S devices are added to generic pm domain, so that entire IP can be powered off/on at appropriate times. Unused DSPs are made to be powered off though they are powered on during ACP pm domain power on sequence. Signed-off-by:
Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com> Reviewed-by:
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