- 11 Apr, 2018 32 commits
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Rex Zhu authored
Acked-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Harry Wentland authored
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Harry Wentland <harry.wentland@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Anthony Koo authored
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Xingyue Tao authored
- Added double buffer mechanism to output CSC so that there's no tearing when adjusting brightness from Radeon settings Signed-off-by:
Xingyue Tao <xingyue.tao@amd.com> Reviewed-by:
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SivapiriyanKumarasamy authored
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SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Anthony Koo authored
Move this out of the HW includes to dc_types.h Signed-off-by:
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Anthony Koo authored
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Xingyue Tao authored
- Video playback shows tearing when adjusting brightness through radeon custom settings. - Now added double buffer mechanism to switch input CSC from register buffer ICSC and COMA - Improved tab alignment Signed-off-by:
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Eric Bernstein authored
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Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
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Bhawanpreet Lakha authored
Correct the types used for printing in logs. This is needed for adding dynamic printing (LINUX), otherwise we get warnings. Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by:
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Vitaly Prosyak authored
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Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
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Eric Yang authored
The current mpcc insert/remove logic does not support updating only a single mpcc. So when pixel alpha changed but no full update we can mistakenly shuffle the mpcc layering order. With this change we will only insert/remove mpcc if there is full update. Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Reviewed-by:
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Mikita Lipski authored
Override the memory input functions for dce120 not to program new registers on dce112. This will fix warnings thrown on Polaris asics. Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Reviewed-by:
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Roman Li authored
Adding assert to prevent possible null deref warning. Only can happen under abnormal circumstances. Signed-off-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
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Tony Cheng authored
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Mikita Lipski authored
Registers are added and defined. Programmed to default values. Stutter level watermark register is being set to calculated value. Urgent level registers are programmed to the same as urgency. The programming of the registers is not expected to have any functional difference in performance. Signed-off-by:
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Julian Parkin authored
Block FP16 scaling in validate_resources codepath. Signed-off-by:
Julian Parkin <jparkin@amd.com> Reviewed-by:
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Eric Bernstein authored
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Mikita Lipski authored
Adding the stutter_entry_wm object to dce_bw_output struct and populating it with bw calculations data Signed-off-by:
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Mikita Lipski authored
amdgpu_dm_display_resume was merged into dm_resume. No need to call these functions separately. Signed-off-by:
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Bhawanpreet Lakha authored
Using the three functions we can print the dceip, vbios and data struct for bandwidth calculations. This is useful for debugging bandwidth calculation issues without a debugger Signed-off-by:
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Dmytro Laktyushkin authored
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Wesley Chalmers <Wesley.Chalmers@amd.com> Acked-by:
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Harry Wentland authored
We shouldn't attempt to read EDID in atomic_check. We really shouldn't even be modifying the connector object, or any other non-state object, but this is a start at least. Moving EDID cleanup to dm_dp_mst_connector_destroy from dm_dp_destroy_mst_connector to ensure the EDID is still available for headless mode. Signed-off-by:
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Nikola Cornij authored
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Nikola Cornij <nikola.cornij@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
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Nikola Cornij authored
Also separate register address initialization between ASICs for the registers that were removed in scaled-down variation of the ASIC. Signed-off-by:
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Yongqiang Sun authored
Some DP panel not detected intermittently due to read dpcd caps failed when doing hot plug. [root cause] DC_HPD_CONNECT_INT_DELAY is set to 0, not delay after HPD toggle and read dpcd data, while some panel need 4ms defer to read. [solution] Add a retry when read failed. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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Tony Cheng authored
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Martin Tsai authored
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Martin Tsai <martin.tsai@amd.com> Reviewed-by:
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Harry Wentland authored
We'd like to use them for reading DCN debug status. Signed-off-by:
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- 10 Apr, 2018 2 commits
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git://people.freedesktop.org/~agd5f/linuxDave Airlie authored
A few fixes for 4.17: - Fix a potential use after free in a error case - Fix pcie lane handling in amdgpu SI dpm - sdma pipeline sync fix - A few vega12 cleanups and fixes - Misc other fixes * 'drm-next-4.17' of git://people.freedesktop.org/~agd5f/linux: drm/amdgpu: Fix memory leaks at amdgpu_init() error path drm/amdgpu: Fix PCIe lane width calculation drm/radeon: Fix PCIe lane width calculation drm/amdgpu/si: implement get/set pcie_lanes asic callback drm/amdgpu: Add support for SRBM selection v3 Revert "drm/amdgpu: Don't change preferred domian when fallback GTT v5" drm/amd/powerply: fix power reading on Fiji drm/amd/powerplay: Enable ACG SS feature drm/amdgpu/sdma: fix mask in emit_pipeline_sync drm/amdgpu: Fix KIQ hang on bare metal for device unbind/bind back v2. drm/amd/pp: Clean header file in vega12_smumgr.c drm/amd/pp: Remove Dead functions on Vega12 drm/amd/pp: silence a static checker warning drm/amdgpu: drop compute ring timeout setting for non-sriov only (v2) drm/amdgpu: fix typo of domain fallback
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Dave Airlie authored
Merge tag 'drm-misc-next-fixes-2018-04-04' of git://anongit.freedesktop.org/drm/drm-misc into drm-next hda_intel: Don't declare azx PM ops if VGA_SWITCHEROO configured (Lukas) Cc: Lukas Wunner <lukas@wunner.de> Cc: Takashi Iwai <tiwai@suse.de> * tag 'drm-misc-next-fixes-2018-04-04' of git://anongit.freedesktop.org/drm/drm-misc: ALSA: hda - Silence PM ops build warning
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- 03 Apr, 2018 6 commits
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Takashi Iwai authored
amdgpu driver checks vgacon_text_force() after some initializations but without cleaning up. This will result in leaks. Move the check of vgacon_text_force() to the beginning of amdgpu_init() for fixing it and also for optimization. Signed-off-by:
Takashi Iwai <tiwai@suse.de> Signed-off-by:
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Alex Deucher authored
The calculation of the lane widths via ATOM_PPLIB_PCIE_LINK_WIDTH_MASK and ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT macros did not increment the resulting value, per the comment in pptable.h ("lanes - 1"), and per usage elsewhere. Port of the radeon fix to amdgpu. Acked-by:Christian König <christian.koenig@amd.com> Acked-by:
Chunming Zhou <david1.zhou@amd.com> Bug: https://bugs.freedesktop.org/show_bug.cgi?id=102553Signed-off-by:
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Paul Parsons authored
Two years ago I tried an AMD Radeon E8860 embedded GPU with the drm driver. The dmesg output included driver warnings about an invalid PCIe lane width. Tracking the problem back led to si_set_pcie_lane_width_in_smc(). The calculation of the lane widths via ATOM_PPLIB_PCIE_LINK_WIDTH_MASK and ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT macros did not increment the resulting value, per the comment in pptable.h ("lanes - 1"), and per usage elsewhere. Applying the increment silenced the warnings. The code has not changed since, so either my analysis was incorrect or the bug has gone unnoticed. Hence submitting this as an RFC. Acked-by:Paul Parsons <lost.distance@yahoo.com> Signed-off-by:
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Alex Deucher authored
Required for dpm setup on some asics. Fixes a NULL dereference on asics that require it. Acked-by:
Abel Garcia Dorta <mercuriete@yahoo.es> Signed-off-by:
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Andrey Grodzovsky authored
Also remove code duplication in write and read regs functions. This also fixes potential missing unlock in amdgpu_debugfs_regs_write in case get_user would fail. v2: Add SRBM mutex locking. v3: Fix TO counter and fix comment location. Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
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Chunming Zhou authored
This reverts commit bbaf1871ea1d7b7021e350a3e8bb1ec8408c2030. Felix reports this commit causes regression. Signed-off-by:
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