- 26 Sep, 2017 40 commits
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Dmytro Laktyushkin authored
Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
Harry Wentland <Harry.Wentland@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
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Tony Cheng authored
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Tony Cheng authored
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Sylvia Tsai authored
- Refacotr PSR to follow correct module pattern - fix eDP only working on sink index 0. Signed-off-by:
Sylvia Tsai <sylvia.tsai@amd.com> Acked-by:
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Zeyu Fan authored
Signed-off-by:
Zeyu Fan <Zeyu.Fan@amd.com> Acked-by:
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Dmytro Laktyushkin authored
This change will cache cursor attributes and reprogram them when enabling cursor after power gating if the attributes were not yet reprogrammed Signed-off-by:
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Charlene Liu authored
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Charlene Liu <charlene.liu@amd.com> Acked-by:
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Yongqiang Sun authored
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Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
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Amy Zhang authored
Signed-off-by:
Amy Zhang <Amy.Zhang@amd.com> Acked-by:
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Dmytro Laktyushkin authored
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Yongqiang Sun authored
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Dmytro Laktyushkin authored
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Harry Wentland authored
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Zeyu Fan authored
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Shirish S authored
dc_commit_surfaces_to_stream() function currently is handle's only one plane at a time. This will not work if multiple planes have to be set to a crtc. The functionality of dc_commit_surfaces_to_stream() with this patch is slit into 1. Accumulate and initialise all the surfaces that needs to be set to a crtc. 2. Update the intialised set of surfaces to the steam in one go. Hence dc_commit_surfaces_to_stream() is renamed to init_surfaces(). Once all the planes requested by user space are initialised, dc_commit_surfaces_to_stream() shall sequentially populates *updates, *flip_addr, *plane_info and *scaling_info for all surfaces. BUG: SWDEV-119421 TEST: (On Chromium OS for Stoney Only) * Chromium UI comes up, on both eDP & DP. * 'new_surface_count' now changes as per user input for e.g for all below run tests its 2, without this patch for the below tests it used to be 1 * Executed below tests to see YUV(underlay) & RGB planes on eDP plane_test --format XR24 --size 500x100 -p --format YV12 --size 500x500 plane_test --format AR24 --size 500x50 -p --format YV12 --size 150x150 plane_test --format AR24 --size 500x50 -p --format YV12 --size 1366x768 Signed-off-by:
Shirish S <shirish.s@amd.com> Signed-off-by:
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Shirish S authored
This patch updates the planes default offsets to the appropriate ones, and aligns the pitch to 64 bits. BUG=SWDEV-119421 TEST=Boots to UI on jadeite TEST= plane_test --format AR24 --size 500x50 -p --format YV12 --size 500x500 plane_test --format AR24 --size 500x50 -p --format YV12 --size 1280x720 plane_test --format AR24 --size 500x50 -p --format YV12 --size 1366x768 Signed-off-by: -
Shirish S authored
This patch populates the YUV surface configurations. Tests: (On Chromium OS for Stoney Only) builds without any errors. Signed-off-by:
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Harry Wentland authored
This will allow us to carry it from check to commit Signed-off-by:
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Harry Wentland authored
This will be needed to clean up context once we add it to private atomic state. Signed-off-by:
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Harry Wentland authored
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Harry Wentland authored
This should make things simpler when we try to rework this later when we pass validate_context from atomic_check to atomic_commit. Signed-off-by:
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Dmytro Laktyushkin authored
Signed-off-by:
Jordan Lazare <Jordan.Lazare@amd.com> Signed-off-by:
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Harry Wentland authored
If we need to update our context we can allocate memory. No need to keep temporary memory for this. Signed-off-by:
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Harry Wentland authored
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Eric Cook authored
- Update BTR/LFC logic so that V_TOTAL_MIN/MAX will take affect on current frame - Add in FreeSync update to MPO code path Signed-off-by:
Eric Cook <Eric.Cook@amd.com> Acked-by:
Anthony Koo <Anthony.Koo@amd.com> Signed-off-by:
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Vitaly Prosyak authored
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Vitaly Prosyak <vitaly.prosyak@amd.com> Acked-by:
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Sylvia Tsai authored
They could differ between ASIC generations Signed-off-by:
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Charlene Liu authored
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Jordan Lazare authored
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Ding Wang authored
- Set stream signal type to be SST when setting non-tile timing on MST tiled display. - Disable MST on sink after disabling MST link. - Enable MST on sink before enabling MST link. Signed-off-by:
Ding Wang <Ding.Wang@amd.com> Acked-by:
Jun Lei <Jun.Lei@amd.com> Signed-off-by:
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Leon Elazar authored
In MST case during removal of remote sink its descriptor pointer wasn't freed corectly. Signed-off-by:
Leon Elazar <leon.elazar@amd.com> Acked-by:
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Yongqiang Sun authored
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Yongqiang Sun authored
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Sylvia Tsai authored
- Adding dm controlled signal type in dc_stream - Adding fallback to dvi signal when output signal is hdmi and the connector type is not Signed-off-by:
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Leon Elazar authored
1. get_ss_info_from_atombios function was allocating the memory populating the provided pointer but them freeing the memory. Since the pointer was return as a valid value, we are trying to free the same memory during clock resource destruction Signed-off-by:
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Zeyu Fan authored
- Remove x,y hotspot from dc_cursor_attributes. Only program it through setPosition. Signed-off-by:
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Charlene Liu authored
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Mario Kleiner authored
Make sure we do not program a hw pageflip inside vblank 'n' iff the atomic flip is comitted while inside the same vblank 'n'. We must defer such a flip by one refresh cycle to vblank 'n+1', unless this is a DRM_MODE_PAGE_FLIP_ASYNC async pageflip, which must always execute as soon as possible. Without this, pageflips programmed via X11 GLX_OML_sync_control extensions glXSwapBuffersMscOML(..., target_msc, ...); call and/or via DRI3/Present PresentPixmap(..., target_msc, ...); request will complete one vblank too early whenever target_msc > current_msc + 1, ie. more than 1 vblank in the future. In such a case, the call of the pageflip ioctl() would be triggered by a queued drmWaitVblank() vblank event, which itself gets dispatched inside the vblank one frame before the target_msc vblank. Testing with this patch does no longer show any problems with OML_sync_control swap scheduling or flip completion timestamps. Tested on R9 380 Tonga. v2: Add acked/r-b by Harry and Michel. v3: Feedback from Andrey: Must not wait an extra frame for DRM_MODE_PAGE_FLIP_ASYNC flips. Signed-off-by:Mario Kleiner <mario.kleiner.de@gmail.com> Acked-by: Harry Wentland <harry.wentland@amd.com> (v1) Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com> Reviewed-by:
Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Cc: Harry Wentland <Harry.Wentland@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
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