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- 16 Aug, 2011 1 commit
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Lothar Waßmann authored
After calling mxs_dma_disable_chan() for a channel, that channel becomes unusable because some controller registers can only be written when the clock is enabled via CLKGATE. Signed-off-by:
Lothar Waßmann <LW@KARO-electronics.de> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- 26 Jul, 2011 2 commits
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Dong Aisheng authored
We met some channels in abnormal state after disable. Reset it to get a clean state. Signed-off-by:
Dong Aisheng <b29396@freescale.com> Cc: Vinod Koul <vinod.koul@intel.com> Cc: Shawn Guo <shawn.guo@linaro.org> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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Axel Lin authored
Signed-off-by:
Axel Lin <axel.lin@gmail.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- 13 Jul, 2011 1 commit
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Shawn Guo authored
In general, the mxs-dma users get separate irq for each channel, but gpmi is special one which has only one irq shared by all gpmi channels. It causes mxs_dma channel allocation function fail for all other gpmi channels except the first one calling into the function. The patch gets request_irq call skipped for NO_IRQ case, and leaves this gpmi specific quirk to gpmi driver to sort out. It will fix above problem if gpmi driver sets chan_irq as gpmi irq for only one channel and NO_IRQ for all the rest channels. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- 02 Mar, 2011 1 commit
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Shawn Guo authored
This patch adds dma support for Freescale MXS-based SoC i.MX23/28, including apbh-dma and apbx-dma. * apbh-dma and apbx-dma are supported in the driver as two mxs-dma instances. * apbh-dma is different between mx23 and mx28, hardware version register is used to differentiate. * mxs-dma supports pio function besides data transfer. The driver uses dma_data_direction DMA_NONE to identify the pio mode, and steals sgl and sg_len to get pio words and numbers from clients. * mxs dmaengine has some very specific features, like sense function and the special NAND support (nand_lock, nand_wait4ready). These are too specific to implemented in generic dmaengine driver. * The driver refers to imx-sdma and only a single descriptor is statically assigned to each channel. Signed-off-by:
Shawn Guo <shawn.guo@freescale.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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