- 05 Jul, 2018 40 commits
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Rex Zhu authored
gfx ip block can call set_powergating_by_smu to set gfx pg state if necessary. Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Rex Zhu authored
Some HW ip blocks need call SMU to enter/leave power gate state. So export common set_powergating_by_smu interface. 1. keep consistent with set_clockgating_by_smu 2. scales easily to powergate other ip(gfx) if necessary Reviewed-by:
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Rex Zhu authored
keep consistent with powergate_uvd/vce/mmhub Reviewed-by:
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Rex Zhu authored
In order to keep consistent with powergate_uvd/vce. Reviewed-by:
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rex zhu authored
fix a typo when convert displayphyclk type. Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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rex zhu authored
powerplay implement hwmgr_function table for all supported asics in order to conceal the asic's detail infomation. so no need to include the smu10_hwmgr.h. Reviewed-by:
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Flora Cui authored
the fence_context and seqno is init in amdgpu_vm_manager_init() & amdgpu_vmid_mgr_init(). remove the amdgpu_vmid_mgr_init() copy. Signed-off-by:
Flora Cui <Flora.Cui@amd.com> Reviewed-by:
Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by:
Chunming Zhou <david1.zhou@amd.com> Signed-off-by:
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Stefan Agner authored
The wrong enum type is used to initialize the result, leading to a warning when using clang: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dp.c:1998:26: warning: implicit conversion from enumeration type 'enum ddc_result' to different enumeration type 'enum dc_status' [-Wenum-conversion] enum dc_status result = DDC_RESULT_UNKNOWN; ~~~~~~ ^~~~~~~~~~~~~~~~~~ 1 warning generated. Initialization of result is unnecessary anyway, just drop the initialization. Signed-off-by:Stefan Agner <stefan@agner.ch> Reviewed-by:
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Andrey Grodzovsky authored
Everything in the flush code path (i.e. waiting for SW queue to become empty) names with *_flush() and everything in the release code path names *_fini() Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Suggested-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
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Andrey Grodzovsky authored
Everything in the flush code path (i.e. waiting for SW queue to become empty) names with *_flush() and everything in the release code path names *_fini() This patch also effect the amdgpu and etnaviv drivers which use those functions. v2: Also pplay the change to vd3. Signed-off-by:
Lucas Stach <l.stach@pengutronix.de> Reviewed-by:
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Tony Cheng authored
use worse case watermark (consider both DCC and VM) to keep golden consistent regardless of DCC Signed-off-by:
Tony Cheng <tony.cheng@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
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Samson Tam authored
Signed-off-by:
Samson Tam <Samson.Tam@amd.com> Reviewed-by:
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Charlene Liu authored
Signed-off-by:
Charlene Liu <charlene.liu@amd.com> Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Tony Cheng authored
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Yongqiang Sun authored
In case of roation, width and height in viewport is difference between viewport and h_active and v_active, while this is not scaling. The right way is check ratios in scaling data, to determine it is a scaling case or not. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
Currently dcn1 will not switch between watermark sets so we can save time by not calculating 3 extra sets. Signed-off-by:
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Dmytro Laktyushkin authored
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Mikita Lipski authored
Moving powerplay functions to a new amdgpu_dm_pp_smu class and cleaning dm_services class from unused headers. Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
Signed-off-by:
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Mikita Lipski authored
The driver is expecting clock frequency in kHz, while SMU returns the values in 10kHz, which causes the bandwidth validation to fail Signed-off-by:
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Mikita Lipski authored
Add more cases for dm_pp clks translator into pp clks so we can pass the right structures to the powerplay. Use clks translator instead of massive switch statement. Signed-off-by:
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Mikita Lipski authored
Set the powerplay debug flag to false for both Windows and Linux to allow the calls to pplib. So we can retrieve the clock values from powerplay instead of using default hardcoded values. Signed-off-by:
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Roman Li authored
- Fixing integer overflow bug in wait_for_fbc_state_changed() - Correct the max value of retries for the corresponding warning Signed-off-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
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Tony Cheng authored
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Dmytro Laktyushkin authored
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Tony Cheng authored
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David Francis authored
As part of hardware certification, read-write access to the link rate, lane count, voltage swing, pre-emphasis, and PHY test pattern of DP connectors is required. This commit adds debugfs files that will correspond to these values. The file operations are not yet implemented: currently writing or reading them does nothing. Signed-off-by:
David Francis <David.Francis@amd.com> Reviewed-by:
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Tony Cheng authored
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Wesley Chalmers authored
DML does not calculate chroma values for RQ when surface is not YUV, but DC will unconditionally use the uninitialized values for HW programming. This does not cause visual corruption since HW will ignore garbage chroma values when surface is not YUV, but causes presubmission tests to fail golden value comparison. Signed-off-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Signed-off-by:
Eryk Brol <eryk.brol@amd.com> Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Acked-by:
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Zheng, XueLai(Eric) authored
Signed-off-by:
XueLai(Eric), Zheng <XueLai.Zheng@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
This will prevent watermarks from lowering when unsafe to do so. Signed-off-by:
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
This fixes incorrect clock caching and by extension fixes the clock reporting. Signed-off-by:
Eric Yang <eric.yang2@amd.com> Acked-by:
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Dmytro Laktyushkin authored
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Charlene Liu authored
Also cleanup command_table2.c. No need for a lot of forward declarations. Signed-off-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
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Wesley Chalmers authored
To ensure tests continue to pass Signed-off-by:
Shahin Khayyer <Shahin.Khayyer@amd.com> Acked-by:
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