- 05 Jul, 2018 40 commits
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Rex Zhu authored
use smu_helper function smu_set_watermarks_for_clocks_ranges in vega12_set_watermarks_for_clocks_ranges. Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Rex Zhu authored
use void * as function parameter type in order for extension. Acked-by:
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rex zhu authored
powerplay can recalculate the number of active display Acked-by:
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rex zhu authored
powerplay can notify smu to recalculates the maximum deep-sleep divider display allowed. Acked-by:
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rex zhu authored
Select the lowest MCLK frequency that is within the tolerable latency defined in DISPALY Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Rex Zhu authored
For HBM, 25us latency is enough for memory clock switch. Acked-by:
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Rex Zhu authored
Convert clock unit 10KHz to KHz as the data sturct defined. e.g. struct pp_clock_with_latency { uint32_t clocks_in_khz; uint32_t latency_in_us; }; Meanwhile revert the same conversion in display side. Acked-by: -
Alex Deucher authored
Was missed when updating the uvd 6 module. Fixes: 1aac3c91 (drm/amdgpu: fix insert nop for UVD6 ring) Reviewed-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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Huang Rui authored
We still use legacy type of gem_object_create, it should update to ttm_bo_type now. Signed-off-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
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Dirk Hohndel (VMware) authored
This is dual licensed under GPL-2.0 or MIT. Acked-by:
Thomas Gleixner <tglx@linutronix.de> Signed-off-by:
Dirk Hohndel (VMware) <dirk@hohndel.org> Signed-off-by:
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Dirk Hohndel (VMware) authored
This is dual licensed under GPL-2.0 or MIT. Acked-by:
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Thomas Zimmermann authored
This patch unifies the naming of DRM functions for reference counting of struct drm_device. The resulting code is more aligned with the rest of the Linux kernel interfaces. Signed-off-by:
Thomas Zimmermann <contact@tzimmermann.org> Signed-off-by:
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Alex Deucher authored
Set the me instance in early init and use that rather than calculating the instance based on the ring pointer. Reviewed-by:
James Zhu <James.Zhu@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Alex Deucher authored
Set the me instance in early init and use that rather than calculating the instance based on the ring pointer. Reviewed-by:
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Alex Deucher authored
Should be using PCIELaneLow for the low clock level. Reviewed-by:
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Alex Deucher authored
Should be mclk rather than sclk. Reviewed-by:
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Alex Deucher authored
Need to swap before doing arthimetic on the values. Reviewed-by:
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Alex Deucher authored
Values need to be swapped on big endian. Reviewed-by:
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Alex Deucher authored
new_active_crtcs is a bitmask, new_active_crtc_count is the actual count. Reviewed-by:
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Alex Deucher authored
The phys and vm versions had the values swapped. Reviewed-by:
Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by:
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Michel Dänzer authored
The parameter was removed. Fixes: a19741e5 "dma_buf: remove device parameter from attach callback v2" Reviewed-by:
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Michel Dänzer authored
To hopefully make the code dealing with GPU vs CPU pages a little clearer. Suggested-by:
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Michel Dänzer authored
Signed-off-by:
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Lyude Paul authored
The other day I was testing one of the HP laptops at my office with an i915/amdgpu hybrid setup and noticed that hotplugging was non-functional on almost all of the display outputs. I eventually discovered that all of the external outputs were connected to the amdgpu device instead of i915, and that the hotplugs weren't being detected so long as the GPU was in runtime suspend. After some talking with folks at AMD, I learned that amdgpu is actually supposed to support hotplug detection in runtime suspend so long as the OEM has implemented it properly in the firmware. On this HP ZBook 15 G4 (the machine in question), amdgpu wasn't managing to find the ATIF handle at all despite the fact that I could see acpi events being sent in response to any hotplugging. After going through dumps of the firmware, I discovered that this machine did in fact support ATIF, but that it's ATIF method lived in an entirely different namespace than this device's handle (the device handle was \_SB_.PCI0.PEG0.PEGP, but ATIF lives in ATPX's handle at \_SB_.PCI0.GFX0). So, fix this by probing ATPX's ACPI parent's namespace if we can't find ATIF elsewhere, along with storing a pointer to the proper handle to use for ATIF and using that instead of the device's handle. This fixes HPD detection while in runtime suspend for this ZBook! v2: Update the comment to reflect how the namespaces are arranged based on the system configuration. (Alex) Signed-off-by:
Lyude Paul <lyude@redhat.com> Signed-off-by:
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Lyude Paul authored
Since it seems that some vendors are storing the ATIF ACPI methods under the same handle that ATPX lives under instead of the device's own handle, we're going to need to be able to retrieve this handle later so we can probe for ATIF there. Signed-off-by:
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Lyude Paul authored
Fix typo. Reviewed-by:
Jim Qu <Jim.Qu@amd.com> Signed-off-by:
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Lyude Paul authored
Currently, there is nothing in amdgpu that actually uses these structs other than amdgpu_acpi.c. Additionally, since we're about to start saving the correct ACPI handle to use for calling ATIF in this struct this saves us from having to handle making sure that the acpi_handle (and by proxy, the type definition for acpi_handle and all of the other acpi headers) doesn't need to be included within the amdgpu_drv struct itself. This follows the example set by amdgpu_atpx_handler.c. Signed-off-by:
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Evan Quan authored
Fix coding style and drop unused variable. Signed-off-by:
Evan Quan <evan.quan@amd.com> Acked-by:
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Evan Quan authored
Thermal support is enabled on vega12. Signed-off-by:
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Evan Quan authored
Set num_displays to 0 and force uclk high as part of the mode set sequence. Signed-off-by:
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Evan Quan authored
This add the apply_clocks_adjust_rules callback which is used to validate the clock settings on a power state change. Signed-off-by:
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Evan Quan authored
Use MAX_NUM_CLOCKS instead of VG12_PSUEDO* macros for the max number of dpm levels. Signed-off-by:
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Evan Quan authored
We don't need to set uclk hard min here because this will be set with other clocks on power state change. Signed-off-by:
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Evan Quan authored
Need to take into account multi-head with synced displays. Signed-off-by:
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Evan Quan authored
On UVD/VCE dpm enabled/disabled, the powergate status will be set as false/true. So that we will not try to ungate/gate them( enable/disable their dpm) again. v2: added check for uvd/vce powergate status before gating v3: fix typo in description v4: warning fix (Alex) Signed-off-by:
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Evan Quan authored
Make sure the clock level set only on dpm enabled. Also uvd/vce/soc clock also changed correspondingly. Signed-off-by:
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Evan Quan authored
So that we do not need to use PPSMC_MSG_GetMin/MaxDpmFreq to get the clock ranges on runtime. Since that causes some problems. Signed-off-by:
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Evan Quan authored
Initialize the soft/hard min/max level correctly and handle the dpm disabled situation. Signed-off-by:
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Evan Quan authored
This workaround is not needed any more. Signed-off-by:
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Evan Quan authored
A new member Vr2_I2C_address is added. Signed-off-by:
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