- 13 Aug, 2024 9 commits
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Tobias Jakobi authored
The struct can be static, as it is only used in this translation unit. Signed-off-by:
Tobias Jakobi <tjakobi@math.uni-bielefeld.de> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Tobias Jakobi authored
The struct can be static, as it is only used in this translation unit. Signed-off-by:
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Remington Brasga authored
A few define's are listed twice with different, incorrect values. This fix sets them appropriately. Signed-off-by:
Remington Brasga <rbrasga@uci.edu> Signed-off-by:
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Colin Ian King authored
There are a several statements with two following semicolons, replace these with just one semicolon. Signed-off-by:
Colin Ian King <colin.i.king@gmail.com> Signed-off-by:
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WangYuli authored
The struct assertion is failed because sparse cannot parse `#pragma pack(push, 1)` and `#pragma pack(pop)` correctly. GCC's output is still 1-byte-aligned. No harm to memory layout. The error can be filtered out by sparse-diff, but sometimes multiple lines queezed into one, making the sparse-diff thinks its a new error. I'm trying to aviod this by fixing errors. Link: https://lore.kernel.org/all/20230620045919.492128-1-suhui@nfschina.com/ Link: https://lore.kernel.org/all/93d10611-9fbb-4242-87b8-5860b2606042@suswa.mountain/ Fixes: 1721bc1b ("drm/amdgpu: Update VF2PF interface") Cc: Dan Carpenter <dan.carpenter@linaro.org> Cc: wenlunpeng <wenlunpeng@uniontech.com> Reported-by:
Su Hui <suhui@nfschina.com> Signed-off-by:
WangYuli <wangyuli@uniontech.com> Signed-off-by:
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Alex Deucher authored
This needs to be set as well if the IB uses atomics. Reviewed-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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Alex Deucher authored
This needs to be set as well if the IB uses atomics. Reviewed-by:
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Hamza Mahfooz authored
To be able to get to the lowest power state when suspending systems with DCN3.5+, we must be in IPS before the display hardware is put into D3cold. So, to ensure that the system always reaches the lowest power state while suspending, force systems that support IPS to enter idle optimizations before entering D3cold. Reviewed-by:
Roman Li <roman.li@amd.com> Signed-off-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Jack Xiao authored
wait memory room until enough before writing mes packets to avoid ring buffer overflow. v2: squash in sched_hw_submission fix Fixes: de324625 ("drm/amdgpu: cleanup MES11 command submission") Fixes: fffe347e ("drm/amdgpu: cleanup MES12 command submission") Signed-off-by:
Jack Xiao <Jack.Xiao@amd.com> Acked-by:
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- 06 Aug, 2024 31 commits
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Arunpravin Paneer Selvam authored
We require this flag AMDGPU_GEM_CREATE_GFX12_DCC or any other kernel level GFX12 DCC flag to differentiate the DCC buffers and other pinned display buffers(which has TTM_PL_FLAG_CONTIGUOUS enabled). If we use the TTM_PL_FLAG_CONTIGUOUS flag for DCC buffers, we may over allocate for all the pinned display buffers unnecessarily that leads to memory allocation failure. Signed-off-by:
Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com> Acked-by:
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Tim Huang authored
This resolves the unchecded return value warning reported by Coverity. Signed-off-by:
Tim Huang <tim.huang@amd.com> Reviewed-by:
Jesse Zhang <jesse.zhang@amd.com> Signed-off-by:
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Tim Huang authored
This resolves the unchecded return value warning reported by Coverity. Signed-off-by:
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Tim Huang authored
This resolves the unchecked return value warning reported by Coverity. Signed-off-by:
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Frank Min authored
correct sdma7 max dw into 8 Signed-off-by:
Frank Min <Frank.Min@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Arunpravin Paneer Selvam authored
Add address alignment support to the DCC VRAM buffers. v2: - adjust size based on the max_texture_channel_caches values only for GFX12 DCC buffers. - used AMDGPU_GEM_CREATE_GFX12_DCC flag to apply change only for DCC buffers. - roundup non power of two DCC buffer adjusted size to nearest power of two number as the buddy allocator does not support non power of two alignments. This applies only to the contiguous DCC buffers. v3:(Alex) - rewrite the max texture channel caches comparison code in an algorithmic way to determine the alignment size. v4:(Alex) - Move the logic from amdgpu_vram_mgr_dcc_alignment() to gmc_v12_0.c and add a new gmc func callback for dcc alignment. If the callback is non-NULL, call it to get the alignment, otherwise, use the default. v5:(Alex) - Set the Alignment to a default value if the callback doesn't exist. - Add the callback to amdgpu_gmc_funcs. v6: - Fix checkpatch warning reported by Intel CI. v7:(Christian) - remove the AMDGPU_GEM_CREATE_GFX12_DCC flag and keep a flag that checks the BO pinning and for a specific hw generation. v8:(Christian) - move this check into gmc_v12_0_get_dcc_alignment. v9: - Fix 32bit build errors Signed-off-by: -
Aric Cyr authored
This version brings along following fixes: - Clean up some files style problems - Program the DET segment when initializing pipes in dcn10_hwseq - Fix overlay with pre-blend color processing - Disable SubVP if Hardware Rotation is Used - Fix few things in DML - Re-enable panel replay feature - Fix null pointer dereference under mst+dsc setup Acked-by:
Tom Chung <chiahsuan.chung@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Signed-off-by:
Wayne Lin <wayne.lin@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Dillon Varone authored
[WHY & HOW] When DRR is active with variable refresh rate, add the ability to block DRR clamped P-State strategies (such as SubVP). Reviewed-by:
Alvin Lee <alvin.lee2@amd.com> Signed-off-by:
Dillon Varone <dillon.varone@amd.com> Signed-off-by:
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Gabe Teeger authored
This reverts commit a1526878 ("drm/amd/display: Avoid overflow assignment in link_dp_cts") Due to regression causing DPMS hang. Reviewed-by:
Alex Hung <alex.hung@amd.com> Signed-off-by:
Gabe Teeger <Gabe.Teeger@amd.com> Signed-off-by:
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Hansen Dsouza authored
[why & how] Add clock source selection control functions based on spec Reviewed-by:
Muhammad Ahmed <ahmed.ahmed@amd.com> Signed-off-by:
Hansen Dsouza <Hansen.Dsouza@amd.com> Signed-off-by:
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Chris Park authored
[Why] Coverity picks up a defect with regards to array underflow. [How] Address coverity issue as recommended. Reviewed-by:
Leo Ma <hanghong.ma@amd.com> Signed-off-by:
Chris Park <chris.park@amd.com> Signed-off-by:
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Fangzhi Zuo authored
[why] Encounter NULL pointer dereference uner mst + dsc setup. BUG: kernel NULL pointer dereference, address: 0000000000000008 PGD 0 P4D 0 Oops: 0000 [#1] PREEMPT SMP NOPTI CPU: 4 PID: 917 Comm: sway Not tainted 6.3.9-arch1-1 #1 124dc55df4f5272ccb409f39ef4872fc2b3376a2 Hardware name: LENOVO 20NKS01Y00/20NKS01Y00, BIOS R12ET61W(1.31 ) 07/28/2022 RIP: 0010:drm_dp_atomic_find_time_slots+0x5e/0x260 [drm_display_helper] Code: 01 00 00 48 8b 85 60 05 00 00 48 63 80 88 00 00 00 3b 43 28 0f 8d 2e 01 00 00 48 8b 53 30 48 8d 04 80 48 8d 04 c2 48 8b 40 18 <48> 8> RSP: 0018:ffff960cc2df77d8 EFLAGS: 00010293 RAX: 0000000000000000 RBX: ffff8afb87e81280 RCX: 0000000000000224 RDX: ffff8afb9ee37c00 RSI: ffff8afb8da1a578 RDI: ffff8afb87e81280 RBP: ffff8afb83d67000 R08: 0000000000000001 R09: ffff8afb9652f850 R10: ffff960cc2df7908 R11: 0000000000000002 R12: 0000000000000000 R13: ffff8afb8d7688a0 R14: ffff8afb8da1a578 R15: 0000000000000224 FS: 00007f4dac35ce00(0000) GS:ffff8afe30b00000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 0000000000000008 CR3: 000000010ddc6000 CR4: 00000000003506e0 Call Trace: <TASK> ? __die+0x23/0x70 ? page_fault_oops+0x171/0x4e0 ? plist_add+0xbe/0x100 ? exc_page_fault+0x7c/0x180 ? asm_exc_page_fault+0x26/0x30 ? drm_dp_atomic_find_time_slots+0x5e/0x260 [drm_display_helper 0e67723696438d8e02b741593dd50d80b44c2026] ? drm_dp_atomic_find_time_slots+0x28/0x260 [drm_display_helper 0e67723696438d8e02b741593dd50d80b44c2026] compute_mst_dsc_configs_for_link+0x2ff/0xa40 [amdgpu 62e600d2a75e9158e1cd0a243bdc8e6da040c054] ? fill_plane_buffer_attributes+0x419/0x510 [amdgpu 62e600d2a75e9158e1cd0a243bdc8e6da040c054] compute_mst_dsc_configs_for_state+0x1e1/0x250 [amdgpu 62e600d2a75e9158e1cd0a243bdc8e6da040c054] amdgpu_dm_atomic_check+0xecd/0x1190 [amdgpu 62e600d2a75e9158e1cd0a243bdc8e6da040c054] drm_atomic_check_only+0x5c5/0xa40 drm_mode_atomic_ioctl+0x76e/0xbc0 [how] dsc recompute should be skipped if no mode change detected on the new request. If detected, keep checking whether the stream is already on current state or not. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by:Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by:
Fangzhi Zuo <Jerry.Zuo@amd.com> Signed-off-by:
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Fudong Wang authored
[Why & How] Add a dc debug option to keep crtc on when ips switch. Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
Fudong Wang <Fudong.Wang@amd.com> Signed-off-by:
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Hansen Dsouza authored
[why & how] Add clock source selection an control functions based on spec Reviewed-by:
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Tom Chung authored
[Why & How] Fixed the replay issues and now re-enable the panel replay feature. Reported-by:
Arthur Borsboom <arthurborsboom@gmail.com> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3344Reviewed-by:
Sun peng Li <sunpeng.li@amd.com> Signed-off-by:
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Dillon Varone authored
[WHY] Currently TR0 (trip 0) is not properly budgeting for urgent latency in DML2.1. This results in overly aggressive prefetch schedules that are vulnerable to request return jitter, resulting in severe underflow at the start of the frame. [HOW] Forcing 3DLUT DMA check to enable causes urgent latency to be budgeted properly into the prefetch schedule, avoiding the vulnerability. Reviewed-by:
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Joshua Aberback authored
[Why] Cursor size can change dynamically at runtime without re-validation, so DML should calculate with the max size cursor to cover all cases. Reviewed-by:
Joshua Aberback <joshua.aberback@amd.com> Signed-off-by:
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Austin Zheng authored
[Why and How] SubVP is not supported when hardware rotation is being used Reviewed-by:
Austin Zheng <Austin.Zheng@amd.com> Signed-off-by:
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Frank Min authored
Without setting cpv bit and 7th ib dw, non-dcc buffer copy will have random corruption So set the cpv bit and clear the 7th ib dw for copy non-dcc buffers Signed-off-by:
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Tao Zhou authored
Instead of printing GPU reset failed. v2: add check for reset_context->src. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
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Tao Zhou authored
Return RMA status without message print. Signed-off-by:
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Fangzhi Zuo authored
Under autonomous mode, source reads dpcd DP_PCON_HDMI_POST_FRL_STATUS for the frl link status. Without dsc passthrough, it serves as bw bottleneck on the entire link, compared with the dp link from source to the converter where dsc is available. Reviewed-by:
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Joshua Ashton authored
As we discussed before[1], soft recovery should be forwarded to userspace, or we can get into a really bad state where apps will keep submitting hanging command buffers cascading us to a hard reset. 1: https://lore.kernel.org/all/bf23d5ed-9a6b-43e7-84ee-8cbfd0d60f18@froggi.es/Signed-off-by:
Joshua Ashton <joshua@froggi.es> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Signed-off-by:
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Yang Wang authored
- amdgpu_ras_error_statistic_ue_count() - amdgpu_ras_error_statistic_ce_count() - amdgpu_ras_error_statistic_de_count() The parameter 'err_addr' is no longer used since following patch. Fixes: a7e8467f ("drm/amdgpu: Remove unused code") Signed-off-by:
Yang Wang <kevinyang.wang@amd.com> Reviewed-by:
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Likun Gao authored
Adding Manual GDB golden setting for gc v12 revision 0 ASIC. Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
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Aurabindo Pillai authored
When programming phantom pipe, since cursor_width is explicity set to 0, this causes calculation logic to trigger overflow for an unsigned int triggering the kernel's UBSAN check as below: [ 40.962845] UBSAN: shift-out-of-bounds in /tmp/amd.EfpumTkO/amd/amdgpu/../display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c:3312:34 [ 40.962849] shift exponent 4294967170 is too large for 32-bit type 'unsigned int' [ 40.962852] CPU: 1 PID: 1670 Comm: gnome-shell Tainted: G W OE 6.5.0-41-generic #41~22.04.2-Ubuntu [ 40.962854] Hardware name: Gigabyte Technology Co., Ltd. X670E AORUS PRO X/X670E AORUS PRO X, BIOS F21 01/10/2024 [ 40.962856] Call Trace: [ 40.962857] <TASK> [ 40.962860] dump_stack_lvl+0x48/0x70 [ 40.962870] dump_stack+0x10/0x20 [ 40.962872] __ubsan_handle_shift_out_of_bounds+0x1ac/0x360 [ 40.962878] calculate_cursor_req_attributes.cold+0x1b/0x28 [amdgpu] [ 40.963099] dml_core_mode_support+0x6b91/0x16bc0 [amdgpu] [ 40.963327] ? srso_alias_return_thunk+0x5/0x7f [ 40.963331] ? CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport+0x18b8/0x2790 [amdgpu] [ 40.963534] ? srso_alias_return_thunk+0x5/0x7f [ 40.963536] ? dml_core_mode_support+0xb3db/0x16bc0 [amdgpu] [ 40.963730] dml2_core_calcs_mode_support_ex+0x2c/0x90 [amdgpu] [ 40.963906] ? srso_alias_return_thunk+0x5/0x7f [ 40.963909] ? dml2_core_calcs_mode_support_ex+0x2c/0x90 [amdgpu] [ 40.964078] core_dcn4_mode_support+0x72/0xbf0 [amdgpu] [ 40.964247] dml2_top_optimization_perform_optimization_phase+0x1d3/0x2a0 [amdgpu] [ 40.964420] dml2_build_mode_programming+0x23d/0x750 [amdgpu] [ 40.964587] dml21_validate+0x274/0x770 [amdgpu] [ 40.964761] ? srso_alias_return_thunk+0x5/0x7f [ 40.964763] ? resource_append_dpp_pipes_for_plane_composition+0x27c/0x3b0 [amdgpu] [ 40.964942] dml2_validate+0x504/0x750 [amdgpu] [ 40.965117] ? dml21_copy+0x95/0xb0 [amdgpu] [ 40.965291] ? srso_alias_return_thunk+0x5/0x7f [ 40.965295] dcn401_validate_bandwidth+0x4e/0x70 [amdgpu] [ 40.965491] update_planes_and_stream_state+0x38d/0x5c0 [amdgpu] [ 40.965672] update_planes_and_stream_v3+0x52/0x1e0 [amdgpu] [ 40.965845] ? srso_alias_return_thunk+0x5/0x7f [ 40.965849] dc_update_planes_and_stream+0x71/0xb0 [amdgpu] Fix this by adding a guard for checking cursor width before triggering the size calculation. Reviewed-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
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Tao Zhou authored
In the convenience of calling it globally. Signed-off-by:
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Hansen Dsouza authored
[why & how] Add new stream and char control functions based on DCCG spec Reviewed-by:
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Michael Strauss authored
[WHY] Overlay works similarly to MPO, but uses global alpha on both planes and sets the desktop as the rear plane instead of the front plane [HOW] Ensure that top plane isn't overlay by checking global alpha before applying the previously added MPO fix Reviewed-by:
Michael Strauss <michael.strauss@amd.com> Signed-off-by:
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Arunpravin Paneer Selvam authored
- Add a new start parameter in trim function to specify exact address from where to start the trimming. This would help us in situations like if drivers would like to do address alignment for specific requirements. - Add a new flag DRM_BUDDY_TRIM_DISABLE. Drivers can use this flag to disable the allocator trimming part. This patch enables the drivers control trimming and they can do it themselves based on the application requirements. v1:(Matthew) - check new_start alignment with min chunk_size - use range_overflows() Signed-off-by:
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Rodrigo Siqueira authored
Add a callback that program the DET segment when initializing pipes. Acked-by:
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