The device_node pointer is returned by of_parse_phandle()  with refcount
incremented. We should use of_node_put() on it when done.

Fixes: 1e747e59 ("pinctrl: rockchip: base regmap supplied by a syscon")
Fixes: 14dee867 ("pinctrl: rockchip: let pmu registers be supplied by a syscon")
Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
Link: https://lore.kernel.org/r/20220307120234.28657-1-linmq006@gmail.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

This node pointer is returned by of_parse_phandle() with refcount
incremented in this function. Calling of_node_put() to avoid
the refcount leak.

Fixes: 32e67eee ("pinctrl: nomadik: Allow prcm_base to be extracted from Device Tree")
Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
Link: https://lore.kernel.org/r/20220307115116.25316-1-linmq006@gmail.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

When krealloc() fails and pctrl->functions is NULL, no error
return code of berlin_pinctrl_build_state() is assigned.
To fix this bug, ret is assigned with -ENOMEM when pctrl->functions
is NULL.
Signed-off-by: Meng Tang <tangmeng@uniontech.com>
Link: https://lore.kernel.org/r/20220303080206.16463-1-tangmeng@uniontech.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

The SC8280XP comes, like all other Qualcomm platforms, with a TLMM
block, so add a driver for it.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220308221132.1423218-2-bjorn.andersson@linaro.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

The Qualcomm SC8280XP platform contains a single block of registers
for the TLMM block. This provides pinconf and pinmux for 228 GPIOs, 2
UFS_RESET pins and one SDC interface.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20220308221132.1423218-1-bjorn.andersson@linaro.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Right now, when a gpio value is set, the actual hardware pin gets set
asynchronously. When linux write the output register, it takes some time
until it is actually propagated to the output shift registers. If that
output port is connected to an I2C mux for example, the linux driver
assumes the I2C bus is already switched although it is not.

Fortunately, there is a single shot mode with a feedback: you can
trigger the single shot and the hardware will clear that bit once it has
finished the clocking and strobed the load signal of the shift
registers. This can take a considerable amount of time though.
Measuremens have shown that it takes up to a whole burst cycle gap which
is about 50ms on the largest setting. Therefore, we have to mark the
output bank as sleepable. To avoid unnecessary waiting, just trigger the
single shot if the value was actually changed.
Signed-off-by: Michael Walle <michael@walle.cc>
Link: https://lore.kernel.org/r/20220226204507.2511633-6-michael@walle.ccSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Make sgpio_output_set() return an error value. Don't just ignore the
return value of any regmap access but propagate it to our callers. Even
if the accesses never fail, this is a preparation patch to add single
shot mode where we need to poll a bit and thus we might get -ETIMEDOUT.
Signed-off-by: Michael Walle <michael@walle.cc>
Link: https://lore.kernel.org/r/20220226204507.2511633-5-michael@walle.ccSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Convert sgpio_clrsetbits() to use regmap_update_bits() and drop the
spinlocks because regmap already takes care of the locking.
Signed-off-by: Michael Walle <michael@walle.cc>
Link: https://lore.kernel.org/r/20220226204507.2511633-4-michael@walle.ccSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

The interrupt ack register has the usual "write one to clear" semantics.
No read-modify-write is required here.

This is also a preparation patch to change the sgpio_clrsetbits() to use
regmap_update_bits() which don't write the value if it is not changed.
Signed-off-by: Michael Walle <michael@walle.cc>
Link: https://lore.kernel.org/r/20220226204507.2511633-3-michael@walle.ccSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Protect any RMW access to the registers by a spinlock.

Fixes: 7e5ea974 ("pinctrl: pinctrl-microchip-sgpio: Add pinctrl driver for Microsemi Serial GPIO")
Signed-off-by: Michael Walle <michael@walle.cc>
Link: https://lore.kernel.org/r/20220226204507.2511633-2-michael@walle.ccSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

In the blamed commit, it removes the duplicate of_node assignment in the
driver. But the driver uses this before calling into of_gpio_dev_init to
determine if it needs to assign an IRQ chip to the GPIO. The fixes
consists in using the platform_get_irq_optional

Fixes: 8a8d6bbe ("pinctrl: Get rid of duplicate of_node assignment in the drivers")
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Link: https://lore.kernel.org/r/20220304144432.3397621-3-horatiu.vultur@microchip.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

iomuxc_snvs from imx6ull supports 2 boot mode and 10 tamper pins.
Probably most users won't use them, causing this error message during boot:
  no groups defined in /soc/bus@2200000/iomuxc-snvs@2290000
This is actually not an error in this case, so reduce the level
accordingly.
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Link: https://lore.kernel.org/r/20220224094243.1376965-1-alexander.stein@ew.tq-group.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

module_platform_driver() makes the code simpler by eliminating
boilerplate code.
Signed-off-by: Srinivas Neeli <srinivas.neeli@xilinx.com>
Link: https://lore.kernel.org/r/20220224043605.26157-1-srinivas.neeli@xilinx.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Add leading space to spdx tag

Replacements
voilates to violates
sepearte to separate
Signed-off-by: Tom Rix <trix@redhat.com>
Link: https://lore.kernel.org/r/20220220162355.3594831-1-trix@redhat.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Extend driving support for I2C pins on SoC mt8195.
This property is already documented in mediatek,mt8183-pinctrl.yaml.
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220216113131.13145-3-tinghan.shen@mediatek.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Use the dev_err_probe() helper to simplify error handling during probe.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20220308100956.2750295-12-wenst@chromium.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Use the dev_err_probe() helper to simplify error handling during probe.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20220308100956.2750295-11-wenst@chromium.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Use the dev_err_probe() helper to simplify error handling during probe.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20220308100956.2750295-10-wenst@chromium.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Some of the MediaTek chips that utilize the Paris pinctrl driver library
support a lower drive strength (<= 1mA) than the standard drive strength
settings (2~16 mA) on certain pins. This was previously supported by the
custom MTK_PIN_CONFIG_DRV_ADV parameter along with the
"mediatek,drive-strength-adv" device tree property.

The drive strength values for this hardware are 125, 250, 500, and 1000 mA,
and can be readily described by the existing "drive-strength-microamp"
property, which then gets parsed by the generic pinconf library into the
parameter PIN_CONFIG_DRIVE_STRENGTH_UA.

Add support for PIN_CONFIG_DRIVE_STRENGTH_UA while keeping the old
custom parameter around for backward compatibility.
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220308100956.2750295-9-wenst@chromium.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

The current code deals with optional features by testing for the
function pointers and returning -ENOTSUPP if it is not valid. This is
done for multiple pin config settings and results in the code that
handles the supporting cases to get indented by one level. This is
aggrevated by the fact that some features require another level of
conditionals.

Instead of assigning the same error code in all unsupported optional
feature cases, simply have that error code as the default, and break
out of the switch/case block whenever a feature is unsupported, or an
error is returned. This reduces indentation by one level for the useful
code.

Also replace the goto statements with break statements. The result is
the same, as the gotos simply exit the switch/case block, which can
also be achieved with a break statement. With the latter the intent
is clear and easier to understand.
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220308100956.2750295-8-wenst@chromium.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Virtual GPIOs do not have any hardware state associated with them. Any
attempt to read back hardware state for these pins result in error
codes.

Skip dumping extra pin config information for these virtual GPIOs.

Fixes: 184d8e13 ("pinctrl: mediatek: Add support for pin configuration dump via debugfs.")
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220308100956.2750295-7-wenst@chromium.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

The caller of mtk_pctrl_show_one_pin() is responsible for printing the
full line. mtk_pctrl_show_one_pin(), called through mtk_pctrl_dbg_show(),
should only produce a string containing the extra information the driver
wants included.

Drop the extra newlines. Also unbreak the line that is only slightly
over 80 characters to make it easier on the eye, and get rid of the
braces now that each block in the conditionals is just one line.

Fixes: 184d8e13 ("pinctrl: mediatek: Add support for pin configuration dump via debugfs.")
Fixes: fb34a9ae ("pinctrl: mediatek: support rsel feature")
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220308100956.2750295-6-wenst@chromium.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

mtk_pconf_group_get(), used to read back pingroup pin config state,
simply returns a set of configs saved from a previous invocation of
mtk_pconf_group_set(). This is an unfiltered, unvalidated set passed
in from the pinconf core, which does not match the current hardware
state.

Since the driver library is designed to have one pin per group, pass
through mtk_pconf_group_get() to mtk_pinconf_get(), to read back the
current pin config state of the only pin in the group.

Also drop the assignment of pin config state to the group.

Fixes: 80525098 ("pinctrl: mediatek: add pinctrl-paris that implements the vendor dt-bindings")
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220308100956.2750295-5-wenst@chromium.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

For mtk_pinconf_get(), the "argument" argument is typically returned by
pinconf_to_config_argument(), which holds the value for a given pinconf
parameter. It certainly should not have the type of "enum pin_config_param",
which describes the type of the pinconf parameter itself.

Change the type to u32, which matches the return type of
pinconf_to_config_argument().

Fixes: 80525098 ("pinctrl: mediatek: add pinctrl-paris that implements the vendor dt-bindings")
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220308100956.2750295-4-wenst@chromium.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

When reading back pin bias settings, if the pin is not in the
corresponding bias state, the function should return -EINVAL.

Fix this in the mediatek-paris pinctrl library so that the read back
state is not littered with bogus a "input bias disabled" combined with
"pull up" or "pull down" states.

Fixes: 80525098 ("pinctrl: mediatek: add pinctrl-paris that implements the vendor dt-bindings")
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220308100956.2750295-3-wenst@chromium.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

The bias-pull-* properties, or PIN_CONFIG_BIAS_PULL_* pin config
parameters, accept optional arguments in ohms denoting the strength of
the pin bias.

Print these values out in debugfs as well.

Fixes: eec45071 ("pinctrl: pinconf-generic: Add flag to print arguments")
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220308100956.2750295-2-wenst@chromium.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

The device_node pointer is returned by of_parse_phandle()  with refcount
incremented. We should use of_node_put() on it when done.

Fixes: a6df410d ("pinctrl: mediatek: Add Pinctrl/GPIO driver for mt8135.")
Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220308071155.21114-1-linmq006@gmail.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

This driver is based on the one for NPCM7xx, because the WPCM450 is a
predecessor of those SoCs. Notable differences:

- On WPCM450, the GPIO registers are not organized in multiple banks,
  but rather placed continually into the same register block. This
  affects how register offsets are computed.
- Pinmux nodes can explicitly select GPIO mode, whereas in the npcm7xx
  driver, this happens automatically when a GPIO is requested.

Some functionality implemented in the hardware was (for now) left unused
in the driver, specifically blinking and pull-up/down.
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reported-by: kernel test robot <lkp@intel.com>
Link: https://lore.kernel.org/r/20220129115228.2257310-6-j.neuschaefer@gmx.netSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

This binding is heavily based on the one for NPCM7xx, because the
hardware is similar. There are some notable differences, however:

- The addresses of GPIO banks are not physical addresses but simple
  indices (0 to 7), because the GPIO registers are not laid out in
  convenient blocks.
- Pinmux settings can explicitly specify that the GPIO mode is used.

Certain pins support blink patterns in hardware. This is currently not
modelled in the DT binding.
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220129115228.2257310-5-j.neuschaefer@gmx.netSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

This driver can have up to two regmaps. If the second one is registered
its debugfs entry will have the same name as the first one and the
following error will be printed:

[    2.242568] debugfs: Directory 'e2004064.pinctrl' with parent 'regmap' already present!

Give the second regmap a name to avoid this.

Fixes: 076d9e71 ("pinctrl: ocelot: convert pinctrl to regmap")
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Colin Foster <colin.foster@in-advantage.com>
Link: https://lore.kernel.org/r/20220216122727.1005041-1-michael@walle.ccSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Prior to commit ad96111e ("pinctrl: ocelot: combine get resource and
ioremap into single call") the resource index was 1, now it is 0. But 0
is the base region for the pinctrl block. Fix it.
I noticed this because there was an error that the memory region was
ioremapped twice.

Fixes: ad96111e ("pinctrl: ocelot: combine get resource and ioremap into single call")
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Colin Foster <colin.foster@in-advantage.com>
Link: https://lore.kernel.org/r/20220216082020.981797-1-michael@walle.ccSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Add i.MX93 pinctrl driver
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/20220228010103.2725893-2-peng.fan@oss.nxp.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Add pinctrl binding doc for i.MX93
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220228010103.2725893-1-peng.fan@oss.nxp.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Change "mediatek,rsel_resistance_in_si_unit" to "mediatek,rsel-resistance-in-si-unit"

Fixes: fb34a9ae ("pinctrl: mediatek: support rsel feature")
Signed-off-by: Guodong Liu <guodong.liu@mediatek.com>
Link: https://lore.kernel.org/r/20220216032124.28067-4-guodong.liu@mediatek.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

This commit includes pinctrl driver for mt8186.
Signed-off-by: Guodong Liu <guodong.liu@mediatek.com>
Link: https://lore.kernel.org/r/20220216032124.28067-3-guodong.liu@mediatek.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

1. This patch adds pinctrl file for mt8186.
2. This patch adds mt8186 compatible node in binding document.
Signed-off-by: Guodong Liu <guodong.liu@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220216032124.28067-2-guodong.liu@mediatek.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Merge tag 'intel-pinctrl-v5.18-1' of gitolite.kernel.org:pub/scm/linux/kernel/git/pinctrl/intel into devel

intel-pinctrl for v5.18-1

* Introduce support for Alder Lake-N (required to revert misplaced ID)
* Add support for Raptor Lake-S
* Add support for Ice Lake-N (MacBookPro16,2)
* Miscellaneous fixes

The following is an automated git shortlog grouped by driver:

alderlake:
 -  Add Intel Alder Lake-N pin controller support
 -  Add Raptor Lake-S ACPI ID

baytrail:
 -  Clear direct_irq_en flag on broken configs

icelake:
 -  Add Ice Lake-N PCH pin controller support

intel:
 -  Fix a glitch when updating IRQ flags on a preconfigured line
 -  fix unexpected interrupt

Place correctly CONFIG_PINCTRL_ST in the Makefile:
 - Place correctly CONFIG_PINCTRL_ST in the Makefile

tigerlake:
 -  Revert "Add Alder Lake-M ACPI ID"

Merge tag 'renesas-pinctrl-for-v5.18-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: renesas: Updates for v5.18 (take two)

  - Share more pin group data, to reduce kernel size and ease review,
  - Improve the pin control table validator,
  - Add support for the new R-Car S4-8 SoC,
  - Miscellaneous fixes and improvements.

Add pins, groups, and functions for the Ethernet Time-Sensitive
Networking (TSN) interfaces on the Renesas R-Car S4-8 (R8A779F0) SoC.

Based on a larger patch in the BSP by LUU HOAI.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/e0a1dc7d2435d28811e3acb361dae050eb3aabc9.1645457792.git.geert+renesas@glider.be

Add pins, groups, and functions for the Quad SPI Controllers on the
Renesas R-Car S4-8 (R8A779F0) SoC.

Based on a larger patch in the BSP by LUU HOAI.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/cd7f7feeabebf268adc9e050e348230e93b40829.1645457792.git.geert+renesas@glider.be