- 09 Dec, 2015 5 commits
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Sudip Mukherjee authored
We were not checking the return value of drm_encoder_init() which can fail. And if it fails then we will be working with an uninitialized encoder. Cc: Daniel Vetter <daniel.vetter@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Sudip Mukherjee <sudip@vectorindia.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1444312681-10149-2-git-send-email-sudipm.mukherjee@gmail.com
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Chris Wilson authored
Userspace can pass in an offset that it presumes the object is located at. The kernel will then do its utmost to fit the object into that location. The assumption is that userspace is handling its own object locations (for example along with full-ppgtt) and that the kernel will rarely have to make space for the user's requests. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> v2: Fixed incorrect eviction found by Michal Winiarski - fix suggested by Chris Wilson. Fixed incorrect error paths causing crash found by Michal Winiarski. (Not published externally) v3: Rebased because of trivial conflict in object_bind_to_vm. Fixed eviction to allow eviction of soft-pinned objects when another soft-pinned object used by a subsequent execbuffer overlaps reported by Michal Winiarski. (Not published externally) v4: Moved soft-pinned objects to the front of ordered_vmas so that they are pinned first after an address conflict happens to avoid repeated conflicts in rare cases (Suggested by Chris Wilson). Expanded comment on drm_i915_gem_exec_object2.offset to cover this new API. v5: Added I915_PARAM_HAS_EXEC_SOFTPIN parameter for detecting this capability (Kristian). Added check for multiple pinnings on eviction (Akash). Made sure buffers are not considered misplaced without the user specifying EXEC_OBJECT_SUPPORTS_48B_ADDRESS. User must assume responsibility for any addressing workarounds. Updated object2.offset field comment again to clarify NO_RELOC case (Chris). checkpatch cleanup. v6: Trivial rebase on latest drm-intel-nightly v7: Catch attempts to pin above the max virtual address size and return EINVAL (Tvrtko). Decouple EXEC_OBJECT_SUPPORTS_48B_ADDRESS and EXEC_OBJECT_PINNED flags, user must pass both flags in any attempt to pin something at an offset above 4GB (Chris, Daniel Vetter). Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Akash Goel <akash.goel@intel.com> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com> Cc: Michal Winiarski <michal.winiarski@intel.com> Cc: Zou Nanhai <nanhai.zou@intel.com> Cc: Kristian Høgsberg <hoegsberg@gmail.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Reviewed-by: Michel Thierry <michel.thierry@intel.com> Acked-by: PDT Signed-off-by: Thomas Daniel <thomas.daniel@intel.com> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1449575707-20933-1-git-send-email-thomas.daniel@intel.com
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Julia Lawall authored
The intel_dvo_dev_ops structures are never modified, so declare them as const. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1449608127-21715-1-git-send-email-Julia.Lawall@lip6.fr
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Rodrigo Vivi authored
GuC has no version for KBL published yet and it is not recommended to load the Skylake one, so let's avoid loading this for now while we don't have the proper GuC firmware for Kabylake. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Alex Dai <yu.dai@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1449622718-21684-1-git-send-email-rodrigo.vivi@intel.com
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Rodrigo Vivi authored
Let's introduce ULT and ULX Kabylake definitions and start using it for a propper DDI buffer translation. v2: Remove extra white space. (Paulo) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
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- 08 Dec, 2015 9 commits
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Imre Deak authored
As described in the code comment, I couldn't set the minimum RPS frequency on my BYT-M B0 to the minimum allowed as reported by Punit. Fix this by clamping the minimum value to the first one that was accepted on my machine. Atm this issue doesn't cause any test failures, since in igt/pm_rps we only check the cached version of the current frequency which is the same what has been set. In the future we'll add checks for the actual frequency too, and for that to pass this fix is necessary. Signed-off-by: Imre Deak <imre.deak@intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1417711175-13271-1-git-send-email-imre.deak@intel.com
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Ville Syrjälä authored
Currently we disable some parts of FDI setup after a failed link training. But despite that we continue with the modeset as if everything is fine. This results in tons of noise from the state checker, and it means we're not following the proper modeset sequence for the rest of crtc enabling, nor for crtc disabling. Ideally we should abort the modeset and follow the proper disable sequence to shut off everything we enabled so far, but that would require a big rework of the modeset code. So instead just leave FDI up and running in its untrained state, and log an error. This is what we do on older platforms too. v2: Fix a typo in the commit message Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1449260570-14670-1-git-send-email-ville.syrjala@linux.intel.com
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Ville Syrjälä authored
Currently we leave the LPT-H VGA dotclock running after turning the pipe/fdi/port/etc. Properly disable the VGA dotclock as specified in the modeset sequence. v2: Fix commit message typo (Paulo) Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1449260534-14551-1-git-send-email-ville.syrjala@linux.intel.com
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Ville Syrjälä authored
Extract the LPT-H VGA dotclock disable to a separate function in anticipation of further use. While at it move the sb_lock locking inwards when enabling the VGA dotclock, as it's only needed to protect the sideband accesses. v2: Keep the PIXCLK_GATE_GATE name for 0 (Paulo) Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1449260494-14449-1-git-send-email-ville.syrjala@linux.intel.com
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Ville Syrjälä authored
Bspec modeset sequence tells us to disable the PCH transcoder and FDI after the CRT port on LPT-H, so let's do that. And the CRT port should be disabled after the pipe, as we do on other PCH platforms too since commit 1ea56e26 ("drm/i915: Disable CRT port after pipe on PCH platforms") commit 00490c22 ("drm/i915: Consider SPLL as another shared pll, v2.") moved the SPLL disable from the .post_disable() hook to some upper level code, so we can just move the CRT port disabling into the .post_disable() hook. If we still had the non-shared SPLL, it would have needed to be moved into the .post_pll_disable() hook. v2: Actually move the CRT port disable to the .post_disable() hook, and amend the commit message with more details (Paulo) v3: Fix typos in commit message (Paulo) Cc: Paulo Zanoni <przanoni@gmail.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1449583548-11896-1-git-send-email-ville.syrjala@linux.intel.com
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Ville Syrjälä authored
Bspec says we should round to closest when computing the LPT-H VGA dotclock, so let's do that. v2: Fix typo in commit message (Paulo) Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1449260421-14243-1-git-send-email-ville.syrjala@linux.intel.com
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Ville Syrjälä authored
When we want to use SPLL for FDI we want SSC, which means we have to disable clock bending for the PCH SSC reference (bend and spread are mutually exclusive). So let's turn off bending when we want spread. In case the BIOS enabled clock bending for some reason we'll just turn it off and enable the spread mode instead. Not sure what happens if the BIOS is actually using the bend source for HDMI at this time, but I suppose it should be no worse than what already happens when we simply turn on the spread. We don't currently use the bend source for anything, and only use the PCH SSC reference for the SPLL to drive FDI (always with spread). v2: Fix the %5 vs %10 fumble for SSCDITHPHASE (Paulo) Add 'WARN_ON(steps % 5 != 0)' sanity check (Paulo) Fix typos in commit message (Paulo) Cc: Paulo Zanoni <przanoni@gmail.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1449260379-14093-1-git-send-email-ville.syrjala@linux.intel.comReviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
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Mika Kuoppala authored
WaRsDoubleRc6WrlWithCoarsePowerGating should be enabled for all Skylakes. Make it so. Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1449505785-20812-2-git-send-email-mika.kuoppala@intel.comSigned-off-by: Jani Nikula <jani.nikula@intel.com>
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Mika Kuoppala authored
There is conflicting info between E0 and F0 steppings for this workarounds. Trust more authoritative source and be conservative and extend also for F0. This prevents numerous (>50) gpu hangs with SKL GT4e during piglit run. References: HSD: gen9lp/2134184 Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1449505785-20812-1-git-send-email-mika.kuoppala@intel.comSigned-off-by: Jani Nikula <jani.nikula@intel.com>
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- 07 Dec, 2015 6 commits
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Rodrigo Vivi authored
'commit 97173eaf ("drm/i915: PSR: Increase idle_frames")' was a mistake. The special case it tried to cover was already being covered by the DP_PSR_NO_TRAIN_ON_EXIT. So this ended up duplicated. So, instead of reverting that let's take this opportunity and unify the idle_frame definition in a single place so we standardize the access and avoid room for that same mistake again. Few changes with this patch: 1. Instead of just respecting the VBT we set a global minumum with max(). So we are sure that we will avoid corner cases in case VBT is doing something we don't understand. 2. Instead of minimum 5 we use 6. When introducing the idle_frames += 4 case we considered that minimum was 2. All because the off-by-one issue. v2: Unified idle_frame definition. Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1449528320-27655-1-git-send-email-rodrigo.vivi@intel.com
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Maarten Lankhorst authored
wait_vblank is already set in intel_plane_atomic_calc_changes for broadwell, waiting for a double vblank is overkill. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1447945645-32005-5-git-send-email-maarten.lankhorst@linux.intel.com
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Maarten Lankhorst authored
On skylake some of the registers are only writable when the correct power wells are enabled. Because of this watermarks have to be updated before the crtc turns off, or you get unclaimed register read and write warnings. This patch needs to be modified slightly to apply to -fixes. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92181Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: stable@vger.kernel.org Cc: Matt Roper <matthew.d.roper@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1447945645-32005-4-git-send-email-maarten.lankhorst@linux.intel.comReviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>
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Maarten Lankhorst authored
This removes pre/post_wm_update from intel_crtc->atomic, and creates atomic state for it in intel_crtc. Changes since v1: - Rebase on top of wm changes. Changes since v2: - Split disable_cxsr into a separate patch. Changes since v3: - Move some of the changes to intel_wm_need_update. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/56603A49.5000507@linux.intel.comReviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Maarten Lankhorst authored
intel_crtc->atomic will be removed later on, move this member to intel_crtc_state. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1447945645-32005-2-git-send-email-maarten.lankhorst@linux.intel.comReviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>
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Zeng Zhaoxiu authored
i915: Replace "hweight8(dev_priv->info.subslice_7eu[i]) != 1" with "!is_power_of_2(dev_priv->info.subslice_7eu[i])" Signed-off-by: Zeng Zhaoxiu <zhaoxiu.zeng@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1449397590-14292-1-git-send-email-zhaoxiu.zeng@gmail.com
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- 04 Dec, 2015 9 commits
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Daniel Vetter authored
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Mika Kuoppala authored
Add Skylake Intel Graphics GT4 PCI IDs v2: Rebase Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1446811876-303-1-git-send-email-mika.kuoppala@intel.com
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Daniel Vetter authored
This reverts commit 6d65ba94. Mika Kuoppala traced down a use-after-free crash in module unload to this commit, because ring->last_context is leaked beyond when the context gets destroyed. Mika submitted a quick fix to patch that up in the context destruction code, but that's too much of a hack. The right fix is instead for the ring to hold a full reference onto it's last context, like we do for legacy contexts. Since this is causing a regression in BAT it gets reverted before we can close this. Cc: Nick Hoath <nicholas.hoath@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: David Gordon <david.s.gordon@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Alex Dai <yu.dai@intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93248Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
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Deepak M authored
The reference clock for BXT is 19.2 MHz not 19.5 MHz, updating the correct value here. Signed-off-by: Deepak M <m.deepak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1449238659-12473-2-git-send-email-m.deepak@intel.com
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Daniel Vetter authored
This was broken in commit 6a8beeff Author: Wayne Boyer <wayne.boyer@intel.com> Date: Wed Dec 2 13:28:14 2015 -0800 drm/i915: Clean up device info structure definitions and I didn't spot this while reviewing. We really need that CI farm up asap! Reported-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Wayne Boyer <wayne.boyer@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
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Chris Wilson authored
In commit 2e1b8730 [v4.2] Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Mon Apr 27 13:41:22 2015 +0100 drm/i915: Convert RPS tracking to a intel_rps_client struct we converted the __i915_wait_request() to take a new intel_rps_client struct (rather than having to pass fake drm_i915_file_private structs). However, due to use of passing a void pointer, I didn't spot one callsite in wait-ioctl was passing the wrong pointer. Fwiw, the impact of this bug is zero. Along the rps path, we always first call list_empty(rps) which when we pass in the wrong pointer always evaluates to false and we return early and never chase the invalid pointers. The user visible impact is then wait-ioctl doesn't get the same waitboosting as the other interfaces (set-domain, throttle), which is a performance concern for the *very* few users of the wait interface. There is also a libdrm_intel patch to use the wait-ioctl for drm_intel_bo_wait_rendering() if anyone feels inclined to review libdrm_intel patches. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> [danvet: Add Chris' explanation for why the impact of this is pretty close to 0.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Daniel Vetter authored
This reverts commit 89f41f4f. It's possible that ->crtc is NULL in here. Noticed by Ville. Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
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Wayne Boyer authored
Beginning with gen7, newer devices repetitively redefine values for the device info structure members. This patch simplifies the structure definitions by grouping member value definitions into the existing GEN7_FEATURES #define and into the new GEN7_LP_FEATURES and HSW_FEATURES #defines. Specifically, GEN_DEFAULT_PIPEOFFSETS and IVB_CURSOR_OFFSETS are added to GEN7_FEATURES and subsequent IVB definitions are simplified. VLV_FEATURES is defined to differentiate and simplify the gen7 low power (LP) devices. HSW_FEATURES is defined and used to simplify all HSW+ devices except for LP. v2: Use VLV_FEATURES for the gen7 low power devices. (Jani) Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Wayne Boyer <wayne.boyer@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1449091694-7681-1-git-send-email-wayne.boyer@intel.com
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Takashi Iwai authored
to_intel_crtc() always returns a non-NULL pointer. Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1448986198-3488-2-git-send-email-tiwai@suse.de
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- 03 Dec, 2015 11 commits
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Maarten Lankhorst authored
As the comment indicates this can only fail gracefully when called from compute_config. Fortunately this is now what's happening, so the fixme can be removed and the DRM_ERROR downgraded. Link: http://patchwork.freedesktop.org/patch/msgid/1448360945-5723-3-git-send-email-maarten.lankhorst@linux.intel.comSigned-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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Alex Goins authored
In intel_prepare_plane_fb, if fb is backed by dma-buf, wait for exclusive fence v2: First commit v3: Remove object_name_lock acquire Move wait from intel_atomic_commit() to intel_prepare_plane_fb() v4: Wait only on exclusive fences, interruptible with no timeout v5: Style tweaks to more closely match rest of file v6: Properly handle interrupted waits v7: No change v8: No change Link: https://patchwork.kernel.org/patch/7704181/Signed-off-by: Alex Goins <agoins@nvidia.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
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Alex Goins authored
If a buffer is backed by dmabuf, wait on its reservation object's exclusive fence before flipping. v2: First commit v3: Remove object_name_lock acquire v4: Move wait ahead of mark_page_flip_active Use crtc->primary->fb to get GEM object instead of pending_flip_obj use_mmio_flip() return true when exclusive fence is attached Wait only on exclusive fences, interruptible with no timeout v5: Move wait from do_mmio_flip to mmio_flip_work_func Style tweaks to more closely match rest of file v6: Change back to unintteruptible wait to match __i915_wait_request due to inability to properly handle interrupted wait. Warn on error code from waiting. v7: No change v8: Test for !reservation_object_signaled_rcu(test_all=FALSE) instead of obj->base.dma_buf->resv->fence_excl Link: https://patchwork.kernel.org/patch/7704181/Signed-off-by: Alex Goins <agoins@nvidia.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
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Nick Hoath authored
Use the first retired request on a new context to unpin the old context. This ensures that the hw context remains bound until it has been written back to by the GPU. Now that the context is pinned until later in the request/context lifecycle, it no longer needs to be pinned from context_queue to retire_requests. This fixes an issue with GuC submission where the GPU might not have finished writing back the context before it is unpinned. This results in a GPU hang. v2: Moved the new pin to cover GuC submission (Alex Dai) Moved the new unpin to request_retire to fix coverage leak v3: Added switch to default context if freeing a still pinned context just in case the hw was actually still using it v4: Unwrapped context unpin to allow calling without a request v5: Only create a switch to idle context if the ring doesn't already have a request pending on it (Alex Dai) Rename unsaved to dirty to avoid double negatives (Dave Gordon) Changed _no_req postfix to __ prefix for consistency (Dave Gordon) Split out per engine cleanup from context_free as it was getting unwieldy Corrected locking (Dave Gordon) v6: Removed some bikeshedding (Mika Kuoppala) Added explanation of the GuC hang that this fixes (Daniel Vetter) v7: Removed extra per request pinning from ring reset code (Alex Dai) Added forced ring unpin/clean in error case in context free (Alex Dai) Signed-off-by: Nick Hoath <nicholas.hoath@intel.com> Issue: VIZ-4277 Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: David Gordon <david.s.gordon@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Alex Dai <yu.dai@intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Alex Dai <yu.dai@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Alex Dai authored
For now, remove the spinlocks that protected the GuC's statistics block and work queue; they are only accessed by code that already holds the global struct_mutex, and so are redundant (until the big struct_mutex rewrite!). The specific problem that the spinlocks caused was that if the work queue was full, the driver would try to spinwait for one jiffy, but with interrupts disabled the jiffy count would not advance, leading to a system hang. The issue was found using test case igt/gem_close_race. The new version will usleep() instead, still holding the struct_mutex but without any spinlocks. v4: Reorganize commit message (Dave Gordon) v3: Remove unnecessary whitespace churn v2: Clean up wq_lock too v1: Clean up host2guc lock as well Signed-off-by: Alex Dai <yu.dai@intel.com> Reviewed-by: Dave Gordon <david.s.gordon@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1449104189-27591-1-git-send-email-yu.dai@intel.comSigned-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Paulo Zanoni authored
There's no need to stop and restart FBC, which is quite expensive as we have to revalidate the CRTC state. After flushing a drawing operation we know the CRTC state hasn't changed, so a nuke (recompress) should be fine. v2: Make it simpler (Chris). v3: Rewrite the patch again due to patch order changes. v4: Rewrite commit message (Chris). Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/
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Paulo Zanoni authored
When running Cinnamon I see way too many pairs of these messages: many per second. Get rid of them as they're just telling us FBC is working as expected. We already have the messages for enable/disable, so we don't really need messages for activation/deactivation. v2: Rebase after changing the patch order. Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/
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Paulo Zanoni authored
Directly call intel_fbc_calculate_cfb_size() in the only place that actually needs it, and use the proper check before removing the stolen node. IMHO, this change makes our code easier to understand. v2: Use drm_mm_node_allocated() (Chris). Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/
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Paulo Zanoni authored
This was already on my TODO list, and was requested both by Chris and Ville, for different reasons. The advantages are avoiding a frequent malloc/free pair, and the locality of having the work structure embedded in dev_priv. The maximum used memory is also smaller since previously we could have multiple allocated intel_fbc_work structs at the same time, and now we'll always have a single one - the one embedded on dev_priv. Of course, we're now using a little more memory on the cases where there's nothing scheduled. The biggest challenge here is to keep everything synchronized the way it was before. Currently, when we try to activate FBC, we allocate a new intel_fbc_work structure. Then later when we conclude we must delay the FBC activation a little more, we allocate a new intel_fbc_work struct, and then adjust dev_priv->fbc.fbc_work to point to the new struct. So when the old work runs - at intel_fbc_work_fn() - it will check that dev_priv->fbc.fbc_work points to something else, so it does nothing. Everything is also protected by fbc.lock. Just cancelling the old delayed work doesn't work because we might just cancel it after the work function already started to run, but while it is still waiting to grab fbc.lock. That's why we use the "dev_priv->fbc.fbc_work == work" check described in the paragraph above. So now that we have a single work struct we have to introduce a new way to synchronize everything. So we're making the work function a normal work instead of a delayed work, and it will be responsible for sleeping the appropriate amount of time itself. This way, after it wakes up it can grab the lock, ask "were we delayed or cancelled?" and then go back to sleep, enable FBC or give up. v2: - Spelling fixes. - Rebase after changing the patch order. - Fix ms/jiffies confusion. Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> (v1) Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/
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Paulo Zanoni authored
This moves the pre-gen4 check from update() to enable(). The HAS_DDI in the original code is not needed since only gen 2/3 have the plane swapping code. v2: Rebase. v3: Extract fbc_on_plane_a_only() (Chris). Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/
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Paulo Zanoni authored
One of the problems with the current code is that it frees the CFB and releases its drm_mm node as soon as we flip FBC's enable bit. This is bad because after we disable FBC the hardware may still use the CFB for the rest of the frame, so in theory we should only release the drm_mm node one frame after we disable FBC. Otherwise, a stolen memory allocation done right after an FBC disable may result in either corrupted memory for the new owner of that memory region or corrupted screen/underruns in case the new owner changes it while the hardware is still reading it. This case is not exactly easy to reproduce since we currently don't do a lot of stolen memory allocations, but I see patches on the mailing list trying to expose stolen memory to user space, so races will be possible. I thought about three different approaches to solve this, and they all have downsides. The first approach would be to simply use multiple drm_mm nodes and freeing the unused ones only after a frame has passed. The problem with this approach is that since stolen memory is rather small, there's a risk we just won't be able to allocate a new CFB from stolen if the previous one was not freed yet. This could happen in case we quickly disable FBC from pipe A and decide to enable it on pipe B, or just if we change pipe A's fb stride while FBC is enabled. The second approach would be similar to the first one, but maintaining a single drm_mm node and keeping track of when it can be reused. This would remove the disadvantage of not having enough space for two nodes, but would create the new problem where we may not be able to enable FBC at the point intel_fbc_update() is called, so we would have to add more code to retry updating FBC after the time has passed. And that can quickly get too complex since we can get invalidate, flush, disable and other calls in the middle of the wait. Both solutions above - and also the current code - have the problem that we unnecessarily free+realloc FBC during invalidate+flush operations even if the CFB size doesn't change. The third option would be to move the allocation/deallocation to enable/disable. This makes sure that the pipe is always disabled when we allocate/deallocate the CFB, so there's no risk that the FBC hardware may read or write to the memory right after it is freed from drm_mm. The downside is that it is possible for user space to change the buffer stride without triggering a disable/enable - only deactivate/activate -, so we'll have to handle this case somehow - see igt's kms_frontbuffer_tracking test, fbc-stridechange subtest. It could be possible to implement a way to free+alloc the CFB during said stride change, but it would involve a lot of book-keeping - exactly as mentioned above - just for on case, so for now I'll keep it simple and just deactivate FBC. Besides, we may not even need to disable FBC since we do CFB over-allocation. Note from Chris: "Starting a fullscreen client that covers a single monitor in a multi-monitor setup will trigger a change in stride on one of the CRTCs (the monitors will be flipped independently).". It shouldn't be a huge problem if we lose FBC on multi-monitor setups since these setups already have problems reaching deep PC states anyway. v2: Rebase after changing the patch order. v3: - Remove references to the stride change case being "uncommon" and paste Chris' example. - Rebase after a change in a previous patch. Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/
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