- 24 Nov, 2011 40 commits
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Timur Tabi authored
On Freescale parts with multiple MSI controllers, the controllers are combined into one "pool" of interrupts. Whenever a device requests an MSI interrupt, the next available interrupt from the pool is selected, regardless of which MSI controller the interrupt is from. This works because each PCI bus has an ATMU to all of CCSR, so any PCI device can access any MSI interrupt register. The fsl,msi property is used to specify that a given PCI bus should only use a specific MSI device. This is necessary, for example, with the Freescale hypervisor, because the MSI devices are assigned to specific partitions. Ideally, we'd like to be able to assign MSI devices to PCI busses within the MSI or PCI layers. However, there does not appear to be a mechanism to do that. Whenever the MSI layer wants to allocate an MSI interrupt to a PCI device, it just calls arch_setup_msi_irqs(). It would be nice if we could register an MSI device with a specific PCI bus. So instead we remember the phandles of each MSI device, and we use that to limit our search for an available interrupt. Whenever we are asked to allocate a new interrupt for a PCI device, we check the fsl,msi property of the PCI bus for that device. If it exists, then as we are looping over all MSI devices, we skip the ones that don't have a matching phandle. Signed-off-by:
Timur Tabi <timur@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala authored
The file name is already scoped by the directory its in. Signed-off-by: -
Kumar Gala authored
P1010RDB & P1023RDS can use the new mpc85xx_common_publish_devices(). Also move 'fsl,srio' into the list of standard buses. Signed-off-by: -
Dmitry Eremin-Solenikov authored
85xx board files have a lot of duplication in *_publish_devices()/ *_declare_of_platform_devices() functions. Merge that into a single function common to most of the boards. Signed-off-by:
Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Signed-off-by:
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Dmitry Eremin-Solenikov authored
Separate handling of CPM2 PIC initialization to mpc85xx_cpm2_pic_init() function. Signed-off-by:
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Dmitry Eremin-Solenikov authored
Traditionally mpc830x_rdb board file searched for mpc8308-pcie devices. However both in-kernel dts from the beginning declared those pcie units as compatible with mpc8314-pci, which is handled by mpc83xx_setup_pci(). Drop special handling for mpc8308 and use common function instead. Signed-off-by:
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Dmitry Eremin-Solenikov authored
Nearly all mpc83xx-based boards have a common piece of code - one that loops over all pci/pcie bridges and registers them. Merge that code into a special function common to all boards. Signed-off-by:
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Dmitry Eremin-Solenikov authored
83xx board files have a lot of duplication in *_declare_of_platform_devices() functions. Merge that into a single function common to most of the boards. The only leftover is mpc834x_itx.c board file which explicitly asks for fsl,pq2pro-localbus, as corresponding bindings don't provide "simple-bus" compatibility in localbus node. Signed-off-by:
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Dmitry Eremin-Solenikov authored
On mpc83xx platform nearly all _init_IRQ functions look alike. They either just setup ipic, or setup ipic and QE PIC. Separate this to special functions to be either referenced from ppc_md, or called from board file. Signed-off-by:
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Timur Tabi authored
The Freescale P1022 has a unique pin muxing "feature" where the DIU video controller's video signals are muxed with 24 of the local bus address signals. When the DIU is enabled, the bulk of the local bus is disabled, preventing access to memory-mapped devices like NOR flash and the pixis FPGA. In this situation, the pixis supports "indirect mode", which allows access to the pixis itself by reading/writing addresses on specific local bus chip selects. CS0 is used to select which pixis register to access, and CS1 is used to read/write the value. To support this, we introduce another board-control child node of the localbus node that contains a 'reg' property for CS0 and CS1. This will produce the correct physical addresses for CS0 and CS1. Signed-off-by:
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Jia Hongtao authored
Power supply for LBC registers is off when system go to deep-sleep state. We save the values of registers before suspend and restore to registers after resume. We removed the last two reservation arrays from struct fsl_lbc_regs for allocating less memory and minimizing the memcpy size. Signed-off-by:
Jiang Yutang <b14898@freescale.com> Signed-off-by:
Jia Hongtao <B38951@freescale.com> Signed-off-by:
Li Yang <leoli@freescale.com> Signed-off-by:
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Jason Jin authored
Current pci/pcie init code will hide the pci/pcie host resource. But did not judge it is host/RC or agent/EP. If configured as agent/EP, we should avoid hiding its resource in the host side. In PCI system, the Programing Interface can be used to judge the host/agent status: Programing Interface = 0: host Programing Interface = 1: Agent In PCIE system, both the Programing Interface and Header type can be used to judge the RC/EP status. Header Type = 0: EP Header Type = 1: RC Signed-off-by:
Jason Jin <Jason.jin@freescale.com> Signed-off-by:
Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by:
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Kumar Gala authored
Update all dts files that support SRIO controllers to match the new fsl,srio device tree binding. Signed-off-by: -
Kumar Gala authored
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Adding of MPIC timer blocks * Dropping "fsl,p5020-IP..." from compatibles for standard blocks * Removed mpic interrupt-parent from dcsr-epu node, just use top level * Removed mpic interrupt-parent from sec nodes, just use top level Signed-off-by: -
Kumar Gala authored
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Adding of MPIC timer blocks * Dropping "fsl,p4080-IP..." from compatibles for standard blocks * Removed mpic interrupt-parent from dcsr-epu node, just use top level * Removed mpic interrupt-parent from sec nodes, just use top level Signed-off-by: -
Kumar Gala authored
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Adding of MPIC timer blocks * Dropping "fsl,p3060-IP..." from compatibles for standard blocks * Removed mpic interrupt-parent from dcsr-epu node, just use top level * Removed mpic interrupt-parent from sec nodes, just use top level * Fixed l3-cache IRQs, we have 2 CPCs, so we should have IRQs for both Signed-off-by: -
Kumar Gala authored
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Adding of MPIC timer blocks * Dropping "fsl,p3041-IP..." from compatibles for standard blocks * Removed mpic interrupt-parent from dcsr-epu node, just use top level * Fixed some dcsr compatiable typo's from 'p43041' to 'p3041' Signed-off-by: -
Kumar Gala authored
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Adding of MPIC timer blocks * Dropping "fsl,p2041-IP..." from compatibles for standard blocks * Removed mpic interrupt-parent from dcsr-epu node, just use top level Signed-off-by: -
Kumar Gala authored
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Updated spi node to new espi binding specification * Renamed 'sdhci' node to 'sdhc' * Changed GPIO compatiable from 'fsl,mpc8572-gpio' to 'fsl,pq3-gpio' as the 'mpc8572' compatiable is to deal with a 'mpc8572' specific to an erratum * Fixed wrong reg offsets for mdio nodes associated with etsec2 & * etsec3 * Dropping "fsl,p2020-IP..." from compatibles for standard blocks Signed-off-by: -
Kumar Gala authored
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Updated spi node to new espi binding specification * Renamed 'sdhci' node to 'sdhc' * Changed GPIO compatiable from 'fsl,mpc8572-gpio' to 'fsl,pq3-gpio' as the 'mpc8572' compatiable is to deal with a 'mpc8572' specific to an erratum * Fixed wrong reg offsets for mdio nodes associated with etsec2 & etsec3 * Dropping "fsl,p2020-IP..." from compatibles for standard blocks Signed-off-by: -
Kumar Gala authored
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Dropping "fsl,p1023-IP..." from compatibles for standard blocks * Removed incorrect power/pmc node, there are no etsec on P1023 Signed-off-by: -
Kumar Gala authored
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Changed GPIO compatiable from 'fsl,mpc8572-gpio' to 'fsl,pq3-gpio' as the 'mpc8572' compatiable is to deal with a 'mpc8572' specific to an erratum * Updated spi node to new espi binding specification * Renamed SDHC node from 'sdhci' to 'sdhc' * Added usb node for 2nd usb controller * Dropping "fsl,p1022-IP..." from compatibles for standard blocks * Fixed bug in local bus range node for CS2, was maping to 0x0 0x0xffa00000 instead of 0xf 0xffa00000 * Fixed localbus reg property should have been 0xf 0xffe05000 Signed-off-by:
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Kumar Gala authored
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Renamed SDHC node from 'sdhci' to 'sdhc' * Added usb node for 2nd usb controller * Dropping "fsl,p1021-IP..." from compatibles for standard blocks Signed-off-by: -
Kumar Gala authored
Signed-off-by: -
Kumar Gala authored
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Dropping "fsl,p1020-IP..." from compatibles for standard blocks * Fixed PCIe interrupt-maps to have proper number of cells * Added mdio node for etsec@26000 * Added usb node for 2nd usb controller Signed-off-by: -
Kumar Gala authored
Signed-off-by: -
Kumar Gala authored
Signed-off-by: -
Kumar Gala authored
Signed-off-by: -
Kumar Gala authored
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Dropping "fsl,p1010-IP..." from compatibles for standard blocks * PCI interrupt map - wrong IRQs for PCI-0 controller * SDHC interrupt sense was wrong Signed-off-by: -
Kumar Gala authored
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Removed CPU properties setup by u-boot to match other .dts * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Moved mdio nodes up one level instead of under tsec nodes * Added GPIO controller node to MPC8572 SoC template * Dropping "fsl,mpc8572-IP..." from compatibles for standard blocks Signed-off-by: -
Kumar Gala authored
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to a standard 2 #address-cells & #size-cells at top-level * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Removed CPU properties setup by u-boot to match other .dts * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Renamed SDHC node from 'sdhci' to 'sdhc' * Dropping "fsl,mpc8569-IP..." from compatibles for standard blocks Signed-off-by: -
Kumar Gala authored
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to a standard 2 #address-cells & #size-cells at top-level * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Removed CPU properties setup by u-boot to match other .dts * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Dropping "fsl,mpc8568-IP..." from compatibles for standard blocks Signed-off-by: -
Kumar Gala authored
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to a standard 2 #address-cells & #size-cells at top-level * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Moved mdio nodes up one level instead of under tsec nodes * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Removed CPU properties setup by u-boot to match other .dts * Added localbus node, but no chipselect details at this point * Added MPIC / PCIe msi node * Dropping "fsl,mpc8548-IP..." from compatibles for standard blocks Signed-off-by: -
Kumar Gala authored
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to a standard 2 #address-cells & #size-cells at top-level * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Removed CPU properties setup by u-boot to match other .dts * Added localbus node, but no chipselect details at this point * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Moved mdio nodes up one level instead of under tsec nodes * Updated ethernet 'model' to 'eTSEC' as that's what on MPC8544 * Dropping "fsl,mpc8544-IP..." from compatibles for standard blocks Signed-off-by: -
Kumar Gala authored
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Added localbus node, but no chipselect details at this point * Reworked PCIe nodes to allow supportin IRQs for controller (errors) * and moved PCI device IRQs down to virtual bridge level * Moved mdio nodes up one level instead of under tsec nodes * Added GPIO controller node to MPC8536 SoC template [ marked as MPC8572 compatiable to get errata handling that applies ] * Added missing cache-line-size & cache-size properties missing from L2-cache node * Added IP level IEEE 1588 / ptp timer node Signed-off-by: -
Kumar Gala authored
Introduce some common components that we can utilize to build up the various PQ3/85xx device trees. Signed-off-by: -
Kumar Gala authored
* set interrupt-parent at root so its not duplicate in every node * Add mpic timers * Move to 4-prop cells for mpic timer Signed-off-by: -
Kumar Gala authored
All eTSEC2 controllers support waking on magic packet so fixup device tree to report that. Signed-off-by: -
Kumar Gala authored
Signed-off-by: -
Kumar Gala authored
The SPI node is out of date with regards to the binding for fsl-espi and driver support. Signed-off-by:
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