- 26 Jun, 2006 40 commits
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Andreas Mohr authored
This one is adding a cpu_relax() that already existed in the i386 version. Signed-off-by:
Andreas Mohr <andi@lisas.de> Signed-off-by:
Andi Kleen <ak@suse.de> Signed-off-by:
Linus Torvalds <torvalds@osdl.org>
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Jan Beulich authored
Defaulting to a value not evenly divisible by four makes little sense, as four values are displayed per line (and hence the rest of the line would otherwise be wasted). Signed-off-by:
Jan Beulich <jbeulich@novell.com> Signed-off-by:
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Jan Beulich authored
With (significantly) more than 10 CPUs online, the column headings drifted off the positions of the column contents with growing CPU numbers. Signed-off-by:
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Andi Kleen authored
When a process changes CPUs while doing the non atomic cpu_local_* operations it might operate on the local_t of a different CPUs. Fix that by disabling preemption. Pointed out by Christopher Lameter Signed-off-by:
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Andi Kleen authored
The APIC ID returned by hard_smp_processor_id can be beyond NR_CPUS and then overflow the x86_cpu_to_apic[] array. Add a check for overflow. If it happens then the slow loop below will catch. Bug pointed out by Doug Thompson Signed-off-by:
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Rohit Seth authored
Getting phys_proc_id and cpu_core_id information to be printed at boot time for AMD processors. Also matching the Node related boot time information that gets printed for Intel and AMD processors for NUMA configurations. Signed-off-by:
Rohit Seth <rohitseth@google.com> Signed-off-by:
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Andi Kleen authored
During some profiling I noticed that default_idle causes a lot of memory traffic. I think that is caused by the atomic operations to clear/set the polling flag in thread_info. There is actually no reason to make this atomic - only the idle thread does it to itself, other CPUs only read it. So I moved it into ti->status. Converted i386/x86-64/ia64 for now because that was the easiest way to fix ACPI which also manipulates these flags in its idle function. Cc: Nick Piggin <npiggin@novell.com> Cc: Tony Luck <tony.luck@intel.com> Cc: Len Brown <len.brown@intel.com> Signed-off-by:
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Andi Kleen authored
No red zone possible/needed on the alternative stack. It caused confusion. Signed-off-by:
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Andrew Morton authored
- Use DMA_32BIT_MASK - Use %z for size_t - 80-cols Cc: Andi Kleen <ak@suse.de> Signed-off-by:
Andrew Morton <akpm@osdl.org> Signed-off-by:
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Jan Beulich authored
- fix an off-by-one error in phys_pmd_init() - prevent phys_pmd_init() from removing mappings established earlier - fix the direct mapping early printk to in fact show the end of the range - remove an apparently orphan comment Signed-off-by:
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Andi Kleen authored
Cc: Jacob Shin <jacob.shin@amd.com> Signed-off-by:
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Jacob Shin authored
Clean up mce_amd.c for readability and remove code no longer needed. Signed-off-by:
Jacob Shin <jacob.shin@amd.com> Signed-off-by:
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Jacob Shin authored
Add support for mce threshold registers found in future AMD family 0x10 processors. Backwards compatible with family 0xF hardware. AK: fixed build on !SMP Signed-off-by:
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Jacob Shin authored
Get rid of /sys/devices/system/threshold directory and move mce_amd thresholding files into the machine sysfs directory -- /sys/devices/system/machinecheck. AK: Fixed warning Signed-off-by:
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Jacob Shin authored
Add support for extended APIC LVT found in future AMD processors. Signed-off-by:
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Andi Kleen authored
Architecture specific configs like this have no business at all in init/Kconfig. This prevents it from being set on x86-64 Pointed out by H.Peter Anvin Signed-off-by:
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Andi Kleen authored
It's like this on SUSE systems. Cc: hpa@zytor.com Signed-off-by:
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Vojtech Pavlik authored
Update my copyright dates in arch/x86-64/kernel/time.c Signed-off-by:
Vojtech Pavlik <vojtech@suse.cz> Signed-off-by:
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Vojtech Pavlik authored
After writing the CFG register, the first value written to the T0_CMP register is the value at which next interrupt should be triggered, every value after that sets the period of the interrupt. For that reason, the code needs to write the value twice - to set both the phase and period. [AK: I had already figured it out by myself, but it's still useful to have a comment for this.] Signed-off-by:
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Vojtech Pavlik authored
This patch makes use of the newly added conversion constants in time.h to x86-64 time.c. The code gets significantly easier to understand. Signed-off-by:
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Vojtech Pavlik authored
Remove #ifdefed code to manually enable HPET on AMD8111, where the BIOS doesn't have ACPI HPET tables and doesn't enable it for us. Signed-off-by:
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Vojtech Pavlik authored
This patch adds the X86_FEATURE_RDTSCP #define, so that kernel code can check for the feature easily and also fixes the location of the "rdtscp" string in the cpuinfo tables. Signed-off-by:
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Vojtech Pavlik authored
Rename oem_force_hpet_timer to apic_is_clustered_box, to give the function a better fitting name - it really isn't at all about HPET. Signed-off-by:
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Vojtech Pavlik authored
In timekeeping code, one often does need to use conversion constants. Naming these leads to code that's easier to understand, showing the reader between which units the conversion is made. Signed-off-by:
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Rohit Seth authored
Most of the fields of cpuinfo are defined in cpuinfo_x86 structure. This patch moves the phys_proc_id and cpu_core_id for each processor to cpuinfo_x86 structure as well. Signed-off-by:
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Jon Mason authored
This patch hooks Calgary into the build, the x86-64 IOMMU initialization paths, and introduces the Calgary specific bits. The implementation draws inspiration from both PPC (which has support for the same chip but requires firmware support which we don't have on x86-64) and gart. Calgary is different from gart in that it support a translation table per PHB, as opposed to the single gart aperture. Changes from previous version: * Addition of boot-time disablement for bus-level translation/isolation (e.g, enable userspace DMA for things like X) * Usage of newer IOMMU abstraction functions Signed-off-by:
Muli Ben-Yehuda <muli@il.ibm.com> Signed-off-by:
Jon Mason <jdmason@us.ibm.com> Signed-off-by:
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Jon Mason authored
This patch creates a new interface for IOMMUs by adding a centralized location for IOMMU allocation (for translation tables/apertures) and IOMMU initialization. In creating these, code was moved around for abstraction, uniformity, and consiceness. Take note of the move of the iommu_setup bootarg parsing code to __setup. This is enabled by moving back the location of the aperture allocation/detection to mem init (which while ugly, was already the location of the swiotlb_init). While a slight departure from the previous patch, I belive this provides the true intention of the previous versions of the patch which changed this code. It also makes the addition of the upcoming calgary code much cleaner than previous patches. [AK: Removed one broken change. iommu_setup still has to be called early] Signed-off-by:
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Jon Mason authored
Based on Andi Kleen's comments on the original Calgary patch, move valid_dma_direction into the calling functions. Signed-off-by:
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Jon Mason authored
swiotlb relies on the gart specific iommu_aperture variable to know if we discovered a hardware IOMMU before swiotlb initialization. Introduce iommu_detected to do the same thing, but in a HW IOMMU neutral manner, in preparation for adding the Calgary HW IOMMU. Signed-Off-By:
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Rohit Seth authored
Minor cleanup patch: Replacing the asm statement with cpuid_count macro(which already provides the same functionality). Signed-off-by:
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Jan Beulich authored
Use abstractions whenever possible. Signed-off-by:
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Andi Kleen authored
pud_offset_k() equivalent to pud_offset() now. Pointed out by Jan Beulich Similar for __pud_offset_ok, which needs a small change in the callers. Signed-off-by:
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Carl-Daniel Hailfinger authored
Clean up arch/{i386,x86_64}/boot/compressed/misc.c a bit to reduce their differences. Should have zero effect on code generation. Signed-off-by:Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Signed-off-by:
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Jan Beulich authored
Add proper conditionals to be able to build with CONFIG_MODULES=n. Signed-off-by:
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Jan Beulich authored
If no unwinding is possible at all for a certain exception instance, fall back to the old style call trace instead of not showing any trace at all. Also, allow setting the stack trace mode at the command line. Signed-off-by:
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Jan Beulich authored
To increase the usefulness of reliable stack unwinding, this adds CFI unwind annotations to many low-level i386 routines. Signed-off-by:
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Jan Beulich authored
These are the i386-specific pieces to enable reliable stack traces. This is going to be even more useful once CFI annotations get added to he assembly code, namely to entry.S. Signed-off-by:
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Jan Beulich authored
Adjust the CFA offset for 64- and 32-bit syscall entries so that the five slots pre-subtracted from the stack pointer do not appear to reside outside of the current frame. Signed-off-by:
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Jan Beulich authored
Change the switching to/from the IRQ stack so that unwind annotations can be added for it without requiring CFA expressions. AK: I cleaned it up a bit, making it unconditional and removing the obsolete DEBUG_INFO full frame code. Signed-off-by:
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Jan Beulich authored
These are the x86_64-specific pieces to enable reliable stack traces. The only restriction with this is that it currently cannot unwind across the interrupt->normal stack boundary, as that transition is lacking proper annotation. Signed-off-by:
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