- 15 Dec, 2023 4 commits
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Donald Robson authored
It is possible to double free the vm_ctx->mmu_ctx object in this function. 630 err_page_table_destroy: --> 631 pvr_mmu_context_destroy(vm_ctx->mmu_ctx); The pvr_vm_context_put() function does: kref_put(&vm_ctx->ref_count, pvr_vm_context_release); Here the pvr_vm_context_release() will call: pvr_mmu_context_destroy(vm_ctx->mmu_ctx); Refactor to an unwind style. Reported-by:
Dan Carpenter <dan.carpenter@linaro.org> Signed-off-by:
Donald Robson <donald.robson@imgtec.com> Reviewed-by:
Maxime Ripard <mripard@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20231213144431.94956-2-donald.robson@imgtec.com
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Donald Robson authored
drivers/gpu/drm/imagination/pvr_vm.c:631 pvr_vm_create_context() error: 'vm_ctx->mmu_ctx' dereferencing possible ERR_PTR() 612 vm_ctx->mmu_ctx = pvr_mmu_context_create(pvr_dev); 613 err = PTR_ERR_OR_ZERO(&vm_ctx->mmu_ctx); ^ The address is never an error pointer so this will always return 0. Remove the ampersand. Reported-by: -
Donald Robson authored
While writing the matching IGT suite I discovered that it's possible to cause a kernel oops when using DRM_IOCTL_PVR_CREATE_HWRT_DATASET when the call to hwrt_init_common_fw_structure() fails. Use an unwind-type error path to avoid cleaning up the object using the the release function before it is fully resolved. Signed-off-by:
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Donald Robson authored
Unwinding loop in error path for this function uses unsigned limit variable, causing the promotion of the signed counter variable. --> 204 for (; pfn >= start_pfn; pfn--) ^^^^^^^^^^^^^^^^ If start_pfn can be zero then this is an endless loop. I've seen this code in other places as well. This loop is slightly off as well. It should decrement pfn on the first iteration. Fix by making the loop limit variables signed. Also fix missing predecrement by modifying to while loop. Reported-by:
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- 13 Dec, 2023 30 commits
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Vignesh Raman authored
Update msm-apq8016-fails, mediatek-mt8173-fails and virtio_gpu-none-fails to include the tests which fail. Signed-off-by:
Vignesh Raman <vignesh.raman@collabora.com> Signed-off-by:
Helen Koike <helen.koike@collabora.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231207091831.660054-11-vignesh.raman@collabora.com
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Vignesh Raman authored
Document the IGT version in the flaky tests reporting template. Acked-by:
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Vignesh Raman authored
virtio-gpu kernel driver reports 16 for count_crtcs which exceeds IGT_MAX_PIPES set to 8 in igt-gpu-tools. This results in below memory corruption, malloc(): corrupted top size Received signal SIGABRT. Stack trace: #0 [fatal_sig_handler+0x17b] #1 [__sigaction+0x40] #2 [pthread_key_delete+0x14c] #3 [gsignal+0x12] #4 [abort+0xd3] #5 [__fsetlocking+0x290] #6 [timer_settime+0x37a] #7 [__default_morecore+0x1f1b] #8 [__libc_calloc+0x161] #9 [drmModeGetPlaneResources+0x44] #10 [igt_display_require+0x194] #11 [__igt_unique____real_main1356+0x93c] #12 [main+0x3f] #13 [__libc_init_first+0x8a] #14 [__libc_start_main+0x85] #15 [_start+0x21] This is fixed in igt-gpu-tools by increasing IGT_MAX_PIPES to 16. https://patchwork.freedesktop.org/series/126327/ Uprev IGT to include the patches which fixes this issue. Acked-by:
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Vignesh Raman authored
There were no artifacts available for virtio job. So make the artifacts available in the pipeline job. Acked-by:
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Vignesh Raman authored
Mediatek 8173 and 8183 SOCs have a separate display controller and GPU with different drivers for each. For mt8173, the GPU driver is powervr and the display driver is mediatek. In the case of mt8183, the GPU driver is panfrost and the display driver is mediatek. Setting IGT_FORCE_DRIVER to panfrost for mt8173 is not the expected driver. So set mediatek for mt8173. Support to test both GPU and display drivers for these ARM SOCs will be added in the next patch series to increase test coverage. Acked-by:
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Vignesh Raman authored
Instead of modifying files in git to enable/disable configs, use scripts/config on the .config file which will be used for building the kernel. Acked-by:
Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Vignesh Raman authored
Enable the following jobs, as the issues noted in the TODO comments have been resolved. This will ensure that these jobs are now included and executed as part of the CI/CD pipeline. msm:apq8016: TODO: current issue: it is not fiding the NFS root. mediatek:mt8173: TODO: current issue: device is hanging. virtio_gpu:none: TODO: current issue: malloc(): corrupted top size. Acked-by:
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Vignesh Raman authored
Mediatek mt8173 board fails to boot with DA9211 regulator disabled. Enable CONFIG_REGULATOR_DA9211=y in arm64.config to fix mt8173 boot issue. Acked-by:
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Vignesh Raman authored
Force db410c to host mode to fix network issue which results in failure to mount root fs via NFS. See https://gitlab.freedesktop.org/gfx-ci/linux/-/commit/cb72a629 Use apq8016-sbc-usb-host.dtb which allows the USB controllers to work in host mode. Acked-by:
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Vignesh Raman authored
/sys/kernel/debug/dri/*/state exist for every atomic KMS driver. We do not test non-atomic drivers, so remove the todo. Acked-by:
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Alex Bee authored
When conditionally checking for heap existence of a certian address in pvr_vm_bind_op_map_init the condition whether the map request comes from a user is incorrect: The context must not be the kernel-context to be a user(space) context and should be looked up in pvr_heaps. That makes addresses coming from userspace not being verfied against the defined ranges and prevents firmware loading for meta cores. Fixes: ff5f643d ("drm/imagination: Add GEM and VM related code") Signed-off-by:
Alex Bee <knaerzche@gmail.com> Reviewed-by:
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Maxime Ripard authored
Even though we were rolling our own custom state for the vc4 HDMI controller driver, we were still using the generic helper to destroy that state. It was mostly working since the underlying state is the first member of our state so the pointers are probably equal in all relevant cases, but it's still fragile so let's fix this properly. Reviewed-by:
Dave Stevenson <dave.stevenson@raspberrypi.com> Signed-off-by:
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Dario Binacchi authored
Adjust the includes to explicitly include the correct headers. Suggested-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Dario Binacchi <dario.binacchi@amarulasolutions.com> Signed-off-by:
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Dario Binacchi authored
Adjust the includes to explicitly include the correct headers. Suggested-by:
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Randy Dunlap authored
Correct spellos reported by codespell. Fix some grammar (as 's' to a few words). Signed-off-by:
Randy Dunlap <rdunlap@infradead.org> Cc: David Airlie <airlied@gmail.com> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Maxime Ripard <mripard@kernel.org> Cc: Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by:
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Randy Dunlap authored
Fix spelling problems as identified by codespell. Signed-off-by:
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Randy Dunlap authored
Correct spelling mistakes that were identified by codespell. Signed-off-by:
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Andy Yan authored
As I am familiar with all the details of vop2 display architecture, I can help review and test all related changes in this subsystem, so add my email here to make sure I get CC'd on rockchip drm changes. Signed-off-by:
Andy Yan <andy.yan@rock-chips.com> Signed-off-by:
Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/20231211120023.1785687-1-andyshrk@163.com
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Andy Yan authored
VOP2 has multiple independent video ports with different feature, so rename VOP_FEATURE_OUTPUT_10BIT to VOP2_VP_FEATURE_OUTPUT_10BIT for more clearly meaning. Signed-off-by:
Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by:
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Andy Yan authored
VOP2 on rk3588: Four video ports: VP0 Max 4096x2160 VP1 Max 4096x2160 VP2 Max 4096x2160 VP3 Max 2048x1080 4 4K Cluster windows with AFBC/line RGB and AFBC-only YUV support 4 4K Esmart windows with line RGB/YUV support Signed-off-by:
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Andy Yan authored
There are 2 HDMI, 2 DP, 2 eDP on rk3588, so add corresponding endpoint definition for it. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
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Andy Yan authored
The vop2 on rk3588 is similar to which on rk356x but with 4 video ports and need to reference more grf modules. Signed-off-by:
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Andy Yan authored
The vop2 need to reference more grf(system grf, vop grf, vo0/1 grf,etc) in the upcoming rk3588. So we rename the current system grf to sys_grf. Signed-off-by:
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Andy Yan authored
We need to setup background delay cycle and prescan delay cycle when a mode is enable to avoid trigger POST_BUF_EMPTY irq on rk3588. Note: RK356x has no such requirement. Signed-off-by:
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Andy Yan authored
Set overlay mode register according to the output mode is yuv or rgb. Signed-off-by:
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Andy Yan authored
The write mask bit is used to make sure when writing config done bit for one VP will not overwrite the other. Unfortunately, the write mask bit is missing on rk3566/8, that means when we write to these bits, it will not take any effect. We need this to make the vop work properly after rk3566/8 variants. Signed-off-by:
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Andy Yan authored
The enable bit and transform offset of cluster windows should be cleared when it work at linear mode, or we may have a iommu fault issue on rk3588 which cluster windows switch between afbc and linear mode. As the cluster windows of rk3568 only supports afbc format so is therefore not affected. Signed-off-by:
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Andy Yan authored
At first we thought the half_block_en bit in AFBCD_CTRL register only work in afbc mode. But the fact is that it control the line buffer in all mode(afbc/tile/linear), so we need configure it in all case. As the cluster windows of rk3568 only supports afbc format so is therefore not affected. Signed-off-by:
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Andy Yan authored
This reverts commit b63a553e. regcache_sync will try to reload the configuration in regcache to hardware, but the registers of 4 Cluster windows and Esmart1/2/3 on the upcoming rk3588 can not be set successfully before internal PD power on. Also it's better to keep the hardware register as it is before we really enable it. So let's revert this version, and keep the first version: commit afa965a4 ("drm/rockchip: vop2: fix suspend/resume") Signed-off-by:
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Andy Yan authored
The output interface related definition can shared between vop and vop2, move them to rockchip_drm_drv.h can avoid duplicated definition. Signed-off-by:
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- 11 Dec, 2023 6 commits
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Uwe Kleine-König authored
It's the ti_sn65dsi86.pwm auxiliary driver that creates the pwmchip, so let the auxiliary device be the parent of the pwm device. Note that getting a reference to the ti-sn65dsi86's pwm using pwm_get() isn't affected by this change as ti_sn65dsi86_add_aux_device() sets the auxiliary device's of_node to that of the main device. Also change PM runtime tracking and diagnostic messages to use that one. After enabling runtime PM operation for the auxiliary device, all works as expected as parent devices are handled just fine. Signed-off-by:
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Tested-by: Nikita Travkin <nikita@trvn.ru> # Acer Aspire 1 Reviewed-by:
Douglas Anderson <dianders@chromium.org> Signed-off-by:
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Elmar Albert authored
G156HAN04.0 is a Color Active Matrix Liquid Crystal Display composed of a TFT LCD panel, a driver circuit, and LED backlight system. The screen format is intended to support the 16:9 FHD, 1920(H) x 1080(V) screen and 16.7M colors (RGB 8-bits) with LED backlight driving circuit. All input signals are LVDS interface compatible. G156HAN04.0 is designed for a display unit of notebook style personal computer and industrial machine. Signed-off-by:
Elmar Albert <ealbert@data-modul.com> Signed-off-by:
Marek Vasut <marex@denx.de> Acked-by:
Neil Armstrong <neil.armstrong@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20231209063714.1381913-2-marex@denx.de
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Elmar Albert authored
Document support for the AUO G156HAN04.0 LVDS display. G156HAN04.0 is a Color Active Matrix Liquid Crystal Display composed of a TFT LCD panel, a driver circuit, and LED backlight system. The screen format is intended to support the 16:9 FHD, 1920(H) x 1080(V) screen and 16.7M colors (RGB 8-bits) with LED backlight driving circuit. All input signals are LVDS interface compatible. G156HAN04.0 is designed for a display unit of notebook style personal computer and industrial machine. Acked-by:
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Michael Trimarchi authored
Tianma TM041XDHG01 utilizes the Ilitek ILI9805 controller. Add this panel's initialzation sequence and timing to ILI9805 driver. Signed-off-by:
Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by:
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Michael Trimarchi authored
The GPM1790A0 panel is based on the Ilitek ILI9805 Controller. Add a driver for it. Signed-off-by:
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Michael Trimarchi authored
Add documentation for "ilitek,ili9805" panel. Signed-off-by:
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