1. 08 Nov, 2019 20 commits
  2. 07 Nov, 2019 20 commits
    • Madalin Bucur's avatar
      net: phy: at803x: add missing dependency on CONFIG_REGULATOR · dddb318b
      Madalin Bucur authored
      Compilation fails on PPC targets as CONFIG_REGULATOR is not set and
      drivers/regulator/devres.c is not compiled in while functions exported
      there are used by drivers/net/phy/at803x.c. Here's the error log:
      
        LD      .tmp_vmlinux1
      drivers/net/phy/at803x.o: In function `at803x_rgmii_reg_set_voltage_sel':
      drivers/net/phy/at803x.c:294: undefined reference to `.rdev_get_drvdata'
      drivers/net/phy/at803x.o: In function `at803x_rgmii_reg_get_voltage_sel':
      drivers/net/phy/at803x.c:306: undefined reference to `.rdev_get_drvdata'
      drivers/net/phy/at803x.o: In function `at8031_register_regulators':
      drivers/net/phy/at803x.c:359: undefined reference to `.devm_regulator_register'
      drivers/net/phy/at803x.c:365: undefined reference to `.devm_regulator_register'
      drivers/net/phy/at803x.o:(.data.rel+0x0): undefined reference to `regulator_list_voltage_table'
      linux/Makefile:1074: recipe for target 'vmlinux' failed
      make[1]: *** [vmlinux] Error 1
      
      Fixes: 2f664823 ("net: phy: at803x: add device tree binding")
      Signed-off-by: default avatarMadalin Bucur <madalin.bucur@nxp.com>
      Reviewed-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      dddb318b
    • Ioana Ciornei's avatar
      dpaa2-eth: add ethtool MAC counters · 991df1fb
      Ioana Ciornei authored
      When a DPNI is connected to a MAC, export its associated counters.
      Ethtool related functions are added in dpaa2_mac for returning the
      number of counters, their strings and also their values.
      Signed-off-by: default avatarIoana Ciornei <ioana.ciornei@nxp.com>
      Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      991df1fb
    • Michael Walle's avatar
      enetc: ethtool: add wake-on-lan callbacks · 88c8562b
      Michael Walle authored
      If there is an external PHY, pass the wake-on-lan request to the PHY.
      Signed-off-by: default avatarMichael Walle <michael@walle.cc>
      Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      88c8562b
    • Michael Walle's avatar
      enetc: add ioctl() support for PHY-related ops · a613bafe
      Michael Walle authored
      If there is an attached PHY try to handle the requested ioctl with its
      handler, which allows the userspace to access PHY registers, for
      example. This will make mii-diag and similar tools work.
      Signed-off-by: default avatarMichael Walle <michael@walle.cc>
      Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      a613bafe
    • Wei Yongjun's avatar
      mlxsw: spectrum: Fix error return code in mlxsw_sp_port_module_info_init() · 630d4e75
      Wei Yongjun authored
      Fix to return negative error code -ENOMEM from the error handling
      case instead of 0, as done elsewhere in this function.
      
      Fixes: 4a7f970f ("mlxsw: spectrum: Replace port_to_module array with array of structs")
      Signed-off-by: default avatarWei Yongjun <weiyongjun1@huawei.com>
      Reviewed-by: default avatarJiri Pirko <jiri@mellanox.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      630d4e75
    • David S. Miller's avatar
      Merge branch 'cxgb4-add-support-for-TC-MQPRIO-Qdisc-Offload' · 69625ea7
      David S. Miller authored
      Rahul Lakkireddy says:
      
      ====================
      cxgb4: add support for TC-MQPRIO Qdisc Offload
      
      This series of patches add support for offloading TC-MQPRIO Qdisc
      to Chelsio T5/T6 NICs. Offloading QoS traffic shaping and pacing
      requires using Ethernet Offload (ETHOFLD) resources available on
      Chelsio NICs. The ETHOFLD resources are configured by firmware
      and taken from the resource pool shared with other Chelsio Upper
      Layer Drivers. Traffic flowing through ETHOFLD region requires a
      software netdev Tx queue (EOSW_TXQ) exposed to networking stack,
      and an underlying hardware Tx queue (EOHW_TXQ) used for sending
      packets through hardware.
      
      ETHOFLD region is addressed using EOTIDs, which are per-connection
      resource. Hence, EOTIDs are capable of storing only a very small
      number of packets in flight. To allow more connections to share
      the the QoS rate limiting configuration, multiple EOTIDs must be
      allocated to reduce packet drops. EOTIDs are 1-to-1 mapped with
      software EOSW_TXQ. Several software EOSW_TXQs can post packets to
      a single hardware EOHW_TXQ.
      
      The series is broken down as follows:
      
      Patch 1 queries firmware for maximum available traffic classes,
      as well as, start and maximum available indices (EOTID) into ETHOFLD
      region, supported by the underlying device.
      
      Patch 2 reworks queue configuration and simplifies MSI-X allocation
      logic in preparation for ETHOFLD queues support.
      
      Patch 3 adds skeleton for validating and configuring TC-MQPRIO Qdisc
      offload. Also, adds support for software EOSW_TXQs and exposes them
      to network stack. Updates Tx queue selection to use fallback NIC Tx
      path for unsupported traffic that can't go through ETHOFLD queues.
      
      Patch 4 adds support for managing hardware queues to rate limit
      traffic flowing through them. The queues are allocated/removed based
      on enabling/disabling TC-MQPRIO Qdisc offload, respectively.
      
      Patch 5 adds Tx path for traffic flowing through software EOSW_TXQ
      and EOHW_TXQ. Also, adds Rx path to handle Tx completions.
      
      Patch 6 updates exisiting SCHED API to configure FLOWC based QoS
      offload. In the existing QUEUE based rate limiting, multiple queues
      sharing a traffic class get the aggreagated max rate limit value.
      On the other hand, in FLOWC based rate limiting, multiple queues
      sharing a traffic class get their own individual max rate limit
      value. For example, if 2 queues are bound to class 0, which is rate
      limited to 1 Gbps, then in QUEUE based rate limiting, both the
      queues get the aggregate max output of 1 Gbps only. In FLOWC based
      rate limiting, each queue gets its own output of max 1 Gbps each;
      i.e. 2 queues * 1 Gbps rate limit = 2 Gbps max output.
      ====================
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      69625ea7
    • Rahul Lakkireddy's avatar
      cxgb4: add FLOWC based QoS offload · 0e395b3c
      Rahul Lakkireddy authored
      Rework SCHED API to allow offloading TC-MQPRIO QoS configuration.
      The existing QUEUE based rate limiting throttles all queues sharing
      a traffic class, to the specified max rate limit value. So, if
      multiple queues share a traffic class, then all the queues get
      the aggregate specified max rate limit.
      
      So, introduce the new FLOWC based rate limiting, where multiple
      queues can share a traffic class with each queue getting its own
      individual specified max rate limit.
      
      For example, if 2 queues are bound to class 0, which is rate limited
      to 1 Gbps, then 2 queues using QUEUE based rate limiting, get the
      aggregate output of 1 Gbps only. In FLOWC based rate limiting, each
      queue gets its own output of max 1 Gbps each; i.e. 2 queues * 1 Gbps
      rate limit = 2 Gbps.
      Signed-off-by: default avatarRahul Lakkireddy <rahul.lakkireddy@chelsio.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      0e395b3c
    • Rahul Lakkireddy's avatar
      cxgb4: add Tx and Rx path for ETHOFLD traffic · 4846d533
      Rahul Lakkireddy authored
      Implement Tx path for traffic flowing through software EOSW_TXQ
      and EOHW_TXQ. Since multiple EOSW_TXQ can post packets to a single
      EOHW_TXQ, protect the hardware queue with necessary spinlock. Also,
      move common code used to generate TSO work request to a common
      function.
      
      Implement Rx path to handle Tx completions for successfully
      transmitted packets.
      Signed-off-by: default avatarRahul Lakkireddy <rahul.lakkireddy@chelsio.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      4846d533
    • Rahul Lakkireddy's avatar
      cxgb4: add ETHOFLD hardware queue support · 2d0cb84d
      Rahul Lakkireddy authored
      Add support for configuring and managing ETHOFLD hardware queues.
      Keep the queue count and MSI-X allocation scheme same as NIC queues.
      ETHOFLD hardware queues are dynamically allocated/destroyed as
      TC-MQPRIO Qdisc offload is enabled/disabled on the corresponding
      interface, respectively.
      Signed-off-by: default avatarRahul Lakkireddy <rahul.lakkireddy@chelsio.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      2d0cb84d
    • Rahul Lakkireddy's avatar
      cxgb4: parse and configure TC-MQPRIO offload · b1396c2b
      Rahul Lakkireddy authored
      Add logic for validation and configuration of TC-MQPRIO Qdisc
      offload. Also, add support to manage EOSW_TXQ, which have 1-to-1
      mapping with EOTIDs, and expose them to network stack.
      
      Move common skb validation in Tx path to a separate function and
      add minimal Tx path for ETHOFLD. Update Tx queue selection to return
      normal NIC Txq to send traffic pattern that can't go through ETHOFLD
      Tx path.
      Signed-off-by: default avatarRahul Lakkireddy <rahul.lakkireddy@chelsio.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      b1396c2b
    • Rahul Lakkireddy's avatar
      cxgb4: rework queue config and MSI-X allocation · 76c3a552
      Rahul Lakkireddy authored
      Simplify queue configuration and MSI-X allocation logic. Use a single
      MSI-X information table for both NIC and ULDs. Remove hard-coded
      MSI-X indices for firmware event queue and non data interrupts.
      Instead, use the MSI-X bitmap to obtain a free MSI-X index
      dynamically. Save each Rxq's index into the MSI-X information table,
      within the Rxq structures themselves, for easier cleanup.
      Signed-off-by: default avatarRahul Lakkireddy <rahul.lakkireddy@chelsio.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      76c3a552
    • Rahul Lakkireddy's avatar
      cxgb4: query firmware for QoS offload resources · ab0367ea
      Rahul Lakkireddy authored
      QoS offload needs Ethernet Offload (ETHOFLD) resources present in the
      NIC. These resources are shared with other ULDs. So, query firmware
      for the available number of traffic classes, as well as, start and
      end indices (EOTID) of the ETHOFLD region.
      Signed-off-by: default avatarRahul Lakkireddy <rahul.lakkireddy@chelsio.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      ab0367ea
    • Eric Dumazet's avatar
      net_sched: gen_estimator: extend packet counter to 64bit · 1c8dd9cb
      Eric Dumazet authored
      I forgot to change last_packets field in struct net_rate_estimator.
      
      Without this fix, rate estimators would misbehave after more
      than 2^32 packets have been sent.
      
      Another solution would be to be careful and only use the
      32 least significant bits of packets counters, but we have
      a hole in net_rate_estimator structure and this looks
      easier to read/maintain.
      
      Fixes: d0083d98 ("net_sched: extend packet counter to 64bit")
      Signed-off-by: default avatarEric Dumazet <edumazet@google.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      1c8dd9cb
    • Chenwandun's avatar
      dpaa2-ptp: fix compile error · 2d791e3b
      Chenwandun authored
      phylink_set_port_modes will be compiled if CONFIG_PHYLINK enabled,
      dpaa2_mac_validate will be compiled if CONFIG_FSL_DPAA2_ETH enabled,
      it should select CONFIG_PHYLINK when dpaa2_mac_validate call
      phylink_set_port_modes
      
      drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.o: In function `dpaa2_mac_validate':
      dpaa2-mac.c:(.text+0x3a1): undefined reference to `phylink_set_port_modes'
      drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.o: In function `dpaa2_mac_connect':
      dpaa2-mac.c:(.text+0x91a): undefined reference to `phylink_create'
      dpaa2-mac.c:(.text+0x94e): undefined reference to `phylink_of_phy_connect'
      dpaa2-mac.c:(.text+0x97f): undefined reference to `phylink_destroy'
      drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.o: In function `dpaa2_mac_disconnect':
      dpaa2-mac.c:(.text+0xa9f): undefined reference to `phylink_disconnect_phy'
      dpaa2-mac.c:(.text+0xab0): undefined reference to `phylink_destroy'
      make: *** [vmlinux] Error 1
      
      Fixes: 71947923 ("dpaa2-eth: add MAC/PHY support through phylink")
      Signed-off-by: default avatarChenwandun <chenwandun@huawei.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      2d791e3b
    • David S. Miller's avatar
      Merge branch '100GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/next-queue · fdc66c3d
      David S. Miller authored
      Jeff Kirsher says:
      
      ====================
      100GbE Intel Wired LAN Driver Updates 2019-11-06
      
      This series contains updates to ice driver only.
      
      Scott adds ethtool -m support so that we can read eeprom data on SFP/OSFP
      modules.
      
      Anirudh updates the return value to properly reflect when SRIOV is not
      supported.
      
      Md Fahad updates the driver to handle a change in the NVM, where the
      boot configuration section was moved to the Preserved Field Area (PFA)
      of the NVM.
      
      Paul resolves an issue when DCBx requests non-contiguous TCs, transmit
      hangs could occur, so configure a default traffic class (TC0) in these
      cases to prevent traffic hangs.  Adds a print statement to notify the
      user when unsupported modules are inserted.
      
      Bruce fixes up the driver unload code flow to ensure we do not clear the
      interrupt scheme until the reset is complete, otherwise a hardware error
      may occur.
      
      Dave updates the DCB initialization to set is_sw_lldp boolean when the
      firmware has been detected to be in an untenable state.  This will
      ensure that the firmware is in a known state.
      
      Michal saves off the PCI state and I/O BARs address after PCI bus reset
      so that after the reset, device registers can be read.  Also adds a NULL
      pointer check to prevent a potential kernel panic.
      
      Mitch resolves an issue where VF's on PF's other than 0 were not seeing
      resets by using the per-PF VF ID instead of the absolute VF ID.
      
      Krzysztof does some code cleanup to remove a unneeded wrapper and
      reduces the code complexity.
      
      Brett reduces confusion by changing the name of ice_vc_dis_vf() to
      ice_vc_reset_vf() to better describe what the function is actually
      doing.
      
      v2: dropped patch 3 "ice: Add support for FW recovery mode detection"
          from the origin al series, while Ani makes changes based on
          community feedback to implement devlink into the changes.
      v3: dropped patch 1 "ice: implement set_eeprom functionality" due to a
          bug found and additional changes will be needed when Ani implements
          devlink in the driver.
      ====================
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      fdc66c3d
    • Andrew Lunn's avatar
      net: dsa: mv8e6xxx: Fix stub function parameters · 64a26007
      Andrew Lunn authored
      mv88e6xxx_g2_atu_stats_get() takes two parameters. Make the stub
      function also take two, otherwise we get compile errors.
      
      Fixes: c5f299d5 ("net: dsa: mv88e6xxx: global1_atu: Add helper for get next")
      Signed-off-by: default avatarAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      64a26007
    • David S. Miller's avatar
      Merge branch 'net-phy-at803x-device-tree-binding' · 16cf4222
      David S. Miller authored
      Michael Walle says:
      
      ====================
      net: phy: at803x device tree binding
      
      Adds a device tree binding to configure the clock and the RGMII voltage.
      
      Changes since v1:
       - rebased to latest net-next
       - renamed "Atheros" to "Qualcomm Atheros"
       - add a new patch to remove config_init() from AR9331
      
      Changes since the RFC:
       - renamed the Kconfig entry to "Qualcomm Atheros.." and reordered the
         item
       - renamed the prefix from atheros to qca
       - use the correct name AR803x (instead of AT803x) in new files and
         dt-bindings.
       - listed the PHY maintainers in the new schema. Hopefully, thats ok.
       - fixed a typo in the bindings schema
       - run dtb_checks and dt_binding_check and fixed the schema
       - dropped the rgmii-io-1v8 property; instead provide two regulators vddh
         and vddio, add one consumer vddio-supply
       - fix the clock settings for the AR8030/AR8035
       - only the AR8031 supports chaning the LDO and the PLL mode in software.
         Check if we have the correct PHY.
       - new patch to mention the AR8033 which is the same as the AR8031 just
         without PTP support
       - new patch which corrects any displayed PHY names and comments. Be
         consistent.
      ====================
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      16cf4222
    • Michael Walle's avatar
      net: phy: at803x: remove config_init for AR9331 · ed7fa2ad
      Michael Walle authored
      According to its datasheet, the internal PHY doesn't have debug
      registers nor MMDs. Since config_init() only configures delays and
      clocks and so on in these registers it won't be needed on this PHY.
      Remove it.
      Signed-off-by: default avatarMichael Walle <michael@walle.cc>
      Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      ed7fa2ad
    • Michael Walle's avatar
      net: phy: at803x: fix the PHY names · 96c36712
      Michael Walle authored
      Fix at least the displayed strings. The actual name of the chip is
      AR803x.
      Signed-off-by: default avatarMichael Walle <michael@walle.cc>
      Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      96c36712
    • Michael Walle's avatar
      net: phy: at803x: mention AR8033 as same as AR8031 · 428061f7
      Michael Walle authored
      The AR8033 is the AR8031 without PTP support. All other registers are
      the same. Unfortunately, they share the same PHY ID. Therefore, we
      cannot distinguish between the one with PTP support and the one without.
      Signed-off-by: default avatarMichael Walle <michael@walle.cc>
      Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      428061f7