1. 08 Jul, 2017 2 commits
  2. 27 Jun, 2017 2 commits
    • Cyrille Pitchen's avatar
      mtd: st_spi_fsm: remove SPINOR_OP_RDSR2 and use SPINOR_OP_RDCR instead · 9447332f
      Cyrille Pitchen authored
      The 35h instruction op code has two aliases/macro definitions:
      - SPINOR_OP_RDCR from include/linux/mtd/spi-nor.h
      - SPINOR_OP_RDSR2 from drivers/mtd/devices/serial_flash_cmds.h
      
      Actually, some manufacturers name the associated internal register Status
      Register 2 whereas other manufacturers name it Configuration Register
      hence the two different macros for the very same instruction op code.
      
      Since the spi-nor.h file is the reference file for all SPI NOR instruction
      op codes, this patch removes the definition of the SPINOR_OP_RDSR2 macro.
      
      Also the SPINOR_OP_RDSR2 macro will be associated to another instruction
      op code in a further patch so we need to avoid a conflict defining this
      macro twice. Indeed the JESD216 rev B specification, defining the SFDP
      tables, also refers to the 3Eh and 3Fh instruction op codes to write/read
      the Status Register 2 on some SPI NOR flash memories, the 35h op code
      still being used to read the Configuration Register/Status Register 2 on
      other memories.
      Signed-off-by: default avatarCyrille Pitchen <cyrille.pitchen@microchip.com>
      Acked-by: default avatarMarek Vasut <marek.vasut@gmail.com>
      9447332f
    • Arnd Bergmann's avatar
      mtd: spi-nor: cqspi: remove duplicate const · 315e9c76
      Arnd Bergmann authored
      The variable was already marked 'const' before the previous
      patch, but the qualifier was in an unusual place, and now the
      extra 'const' causes a harmless warning:
      
      drivers/mtd/spi-nor/cadence-quadspi.c:1286:34: error: duplicate 'const' declaration specifier [-Werror=duplicate-decl-specifier]
      
      This removes the other 'const' instead.
      
      Fixes: f993c123 ("mtd: spi-nor: cqspi: make of_device_ids const")
      Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
      Signed-off-by: default avatarCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
      315e9c76
  3. 26 Jun, 2017 2 commits
  4. 23 Jun, 2017 2 commits
  5. 22 Jun, 2017 7 commits
  6. 21 Jun, 2017 1 commit
    • Cédric Le Goater's avatar
      mtd: spi-nor: aspeed: configure chip window on AHB bus · 7ef0e5e1
      Cédric Le Goater authored
      The segment registers of the SMC controller provide a way to configure
      the mapping windows of the chips on the AHB bus. The settings are
      required to be correct when the controller operates in Command mode,
      which is the case for DMAs and the LPC mapping.
      
      This tries to set the segment registers of each chip depending on the
      size of the flash device and depending on the previous segment
      settings, in order to have a contiguous window across multiple chips.
      
      Unfortunately, the AST2500 SPI controller has a bug and it is not
      possible to configure a full 128MB window for a chip of the same
      size. The window size needs to be restricted to 120MB. This issue only
      applies to CE0.
      Signed-off-by: default avatarCédric Le Goater <clg@kaod.org>
      Reviewed-by: default avatarMarek Vasut <marek.vasut@gmail.com>
      Signed-off-by: default avatarCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
      7ef0e5e1
  7. 20 Jun, 2017 7 commits
  8. 13 Jun, 2017 1 commit
  9. 08 Jun, 2017 3 commits
  10. 01 Jun, 2017 4 commits
  11. 22 May, 2017 9 commits