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    • Lars-Peter Clausen's avatar
      iio:adc: Add Xilinx XADC driver · bdc8cda1
      Lars-Peter Clausen authored
      The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx.
      The XADC has a DRP interface for communication. Currently two different
      frontends for the DRP interface exist. One that is only available on the ZYNQ
      family as a hardmacro in the SoC portion of the ZYNQ. The other one is available
      on all series 7 platforms and is a softmacro with a AXI interface. This driver
      supports both interfaces and internally has a small abstraction layer that hides
      the specifics of these interfaces from the main driver logic.
      
      The ADC has a couple of internal channels which are used for voltage and
      temperature monitoring of the FPGA as well as one primary and up to 16 channels
      auxiliary channels for measuring external voltages. The external auxiliary
      channels can either be directly connected each to one physical pin on the FPGA
      or they can make use of an external multiplexer which is responsible for
      multiplexing the external signals onto one pair of physical pins.
      
      The voltage and temperature monitoring channels also have an event capability
      which allows to generate a interrupt when their value falls below or raises
      above a set threshold.
      
      Buffered sampling mode is supported by the driver, but only for AXI-XADC since
      the ZYNQ XADC interface does not have capabilities for supporting buffer mode
      (no end-of-conversion interrupt). If buffered mode is supported the driver will
      register two triggers. One "xadc-samplerate" trigger which will generate samples
      with the configured samplerate. And one "xadc-convst" trigger which will
      generate one sample each time the CONVST (conversion start) signal is asserted.
      Signed-off-by: default avatarLars-Peter Clausen <lars@metafoo.de>
      Signed-off-by: default avatarJonathan Cameron <jic23@kernel.org>
      bdc8cda1
  27. 28 Feb, 2014 1 commit
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  30. 17 Aug, 2013 1 commit
    • Oleksandr Kozaruk's avatar
      iio: twl6030-gpadc: TWL6030, TWL6032 GPADC driver · 1696f364
      Oleksandr Kozaruk authored
      The GPADC is general purpose ADC found on TWL6030, and TWL6032 PMIC,
      known also as Phoenix and PhoenixLite.
      
      The TWL6030 and TWL6032 have GPADC with 17 and 19 channels
      respectively. Some channels have current source and are used for
      measuring voltage drop on resistive load for detecting battery ID
      resistance, or measuring voltage drop on NTC resistors for external
      temperature measurements. Some channels measure voltage, (i.e. battery
      voltage), and have voltage dividers, thus, capable to scale voltage.
      Some channels are dedicated for measuring die temperature.
      
      Some channels are calibrated in 2 points, having offsets from ideal
      values kept in trim registers. This is used to correct measurements.
      
      The differences between GPADC in TWL6030 and TWL6032:
      - 10 bit vs 12 bit ADC;
      - 17 vs 19 channels;
      - channels have different purpose(i.e. battery voltage
        channel 8 vs channel 18);
      - trim values are interpreted differently.
      
      Based on the driver patched from Balaji TK, Graeme Gregory, Ambresh K,
      Girish S Ghongdemath.
      Signed-off-by: default avatarBalaji T K <balajitk@ti.com>
      Signed-off-by: default avatarGraeme Gregory <gg@slimlogic.co.uk>
      Signed-off-by: default avatarOleksandr Kozaruk <oleksandr.kozaruk@ti.com>
      Signed-off-by: default avatarJonathan Cameron <jic23@kernel.org>
      1696f364
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