- 06 Aug, 2020 11 commits
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Evan Quan authored
Add Sienna Cichlid gpu metrics export interface. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Evan Quan authored
Add Navi1x gpu metrics export interface. Signed-off-by:
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Evan Quan authored
Although it does not bring any problem for now, the coming gpu metrics interface needs to handle them differently based on the asic type. Signed-off-by:
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Evan Quan authored
Add Arcturus gpu metrics export interface. Signed-off-by:
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Evan Quan authored
This will be shared around all SMU V11 asics. Signed-off-by:
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Evan Quan authored
A new interface for UMD to retrieve gpu metrics data. V2: rich the documentation Signed-off-by:
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Evan Quan authored
Thus we can provide an interface for UMD to retrieve gpu metrics data. V2: better naming and comments V3: two structures created for dGPU and APU separately V4: add driver attached timestamp Signed-off-by:
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Colin Ian King authored
There is a spelling mistake in a dev_warn message. Fix it. Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Evan Quan authored
For Arcturus, the softmin/max settings from driver are permitted on the latest(54.26 later) SMU firmware. Thus enabling them in driver. Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Signed-off-by:
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Philip Yang authored
If multiple process share system memory through /dev/shm, KFD allocate memory should not fail if it reaches the system memory limit because one copy of physical system memory are shared by multiple process. Add module parameter no_system_mem_limit to provide user option to disable system memory limit check at runtime using sysfs or during driver module init using kernel boot argument. By default the system memory limit is on. Print out debug message to warn user if KFD allocate memory failed because system memory reaches limit. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Tianjia Zhang authored
On an error exit path, a negative error code should be returned instead of a positive return value. Fixes: 9e869063 ("drm/amd/display: Move iteration out of dm_update_planes") Cc: Leo Li <sunpeng.li@amd.com> Signed-off-by:
Tianjia Zhang <tianjia.zhang@linux.alibaba.com> Signed-off-by:
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- 04 Aug, 2020 29 commits
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Rikard Falkeborn authored
The only usage of dcn30_res_pool_funcs is to assign its address to a const pointer. Make it const to allow the compiler to put it in read-only memory. Signed-off-by:
Rikard Falkeborn <rikard.falkeborn@gmail.com> Signed-off-by:
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Rikard Falkeborn authored
The only usage of dcn21_res_pool_funcs is to assign its address to a const pointer. Make it const to allow the compiler to put it in read-only memory. Signed-off-by:
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Rikard Falkeborn authored
The only usage of dcn20_res_pool_funcs is to assign its address to a const pointer. Make it const to allow the compiler to put it in read-only memory. Signed-off-by:
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Dan Carpenter authored
The if statement wasn't indented so it's confusing. Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
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Alex Deucher authored
It's related to the memory manager so move it there. v2: inline the structure Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Alex Deucher authored
It's related to the memory manager so move it there. Reviewed-by:
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Alex Deucher authored
It's more related to memory management than memory controller. Reviewed-by:
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Alex Deucher authored
I suspect the only reason this was set was to avoid touching the display related registers on arcturus. Someone should double check this on arcturus with S3. Reviewed-by:
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Alex Deucher authored
We never use them. Reviewed-by:
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Alex Deucher authored
The new helper centralizes the logic in one place. Reviewed-by:
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Alex Deucher authored
The new helper centralizes the logic in one place. Reviewed-by:
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Alex Deucher authored
The new helper centralizes the logic in one place. Reviewed-by:
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Alex Deucher authored
The new helper centralizes the logic in one place. Reviewed-by:
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Alex Deucher authored
The new helper centralizes the logic in one place. Reviewed-by:
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Alex Deucher authored
This adds a new gmc callback to get the size reserved by the pre-OS console and provides a helper function for use by gmc IP drivers. Reviewed-by:
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Alex Deucher authored
This will allow us to split the allocation for systems where we have to keep the stolen memory around to avoid S3 issues. This way we don't waste as much memory and still avoid any screen artifacts during the bios to driver transition. Reviewed-by:
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Alex Deucher authored
Rather than leaving this as a gmc v9 specific hack. Reviewed-by:
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Alex Deucher authored
Since that is where we store the other data related to the stolen vga memory. Reviewed-by:
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Alex Deucher authored
Rather than open coding it everywhere. Reviewed-by:
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Alex Deucher authored
Should be functionally the same since nothing else is allocated at that point, but let's be exact. Reviewed-by:
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Alex Deucher authored
Just return early to match other bo_create functions. v2: check if the bo_ptr is NULL rather than checking the size. Reviewed-by:
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Alex Deucher authored
The i2c init/fini functions just register the i2c adapter. There is no need to call them during hw init/fini. They only need to be called once per driver init/fini. The previous behavior broke runtime pm because we unregistered the i2c adapter during suspend. Tested-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
Kevin Wang <kevin1.wang@amd.com> Signed-off-by:
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Aric Cyr authored
Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
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Anthony Koo authored
| [Header Changes] | - Reworked the FW versioning to include hotfix | and test bits Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Alvin Lee authored
[Why] When changing pixel formats for HDR (e.g. ARGB -> FP16) there are configurations that change from 2 pipes to 1 pipe. In these cases, it seems that disconnecting MPCC and doing a surface update at the same time(after unlocking) causes some registers to be updated slightly faster than others after unlocking (e.g. if the pixel format is updated to FP16 before the new surface address is programmed, we get corruption on the screen because the pixel formats aren't matching). We separate disconnecting MPCC from the rest of the pipe programming sequence to prevent this. [How] Move MPCC disconnect into separate operation than the rest of the pipe programming. Signed-off-by:
Alvin Lee <alvin.lee2@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Victor Lu authored
[why] There's currently no method to enable multi-stream synchronization from userspace and we don't check the VSDB bits to know whether or not specific displays should have the feature enable. [how] Add a debugfs entry that controls a new DM debug option, "force_timing_sync". This debug option will set on any newly created stream following the change to the debug option. Expose a new interface from DC that performs the timing sync and a helper to the "force_timing_sync" debugfs that iterates over the current streams and modifies the current synchornization state and grouping. Example usage to force a resync (from an X based desktop): echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync xset dpms force off && xset dpms force on Signed-off-by:
Victor Lu <victorchengchi.lu@amd.com> Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Signed-off-by:
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Igor Kravchenko authored
[why] Display goes blank after driver installation. Aux tuning parameters must be used for 2.x only. Wrong dc_golden_table offset was used. [How] Implement a new enc3_hw_init function without VBIOS constants usage to be called for 3.x Calculate dc_golden_table offset using sum of base dce_info offset and golden table offset Signed-off-by:
Igor Kravchenko <Igor.Kravchenko@amd.com> Reviewed-by:
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George Shen authored
[Why] During SetPathMode and UpdatePlanes, the plane state can be null. We default to linear swizzle mode when plane state is null. This resulted in bandwidth validation failing when trying to set 8K60 mode (which previously passed validation during rebuild timing list). [How] Change the default swizzle mode from linear to 4kb_s and update pitch accordingly. Signed-off-by:
George Shen <george.shen@amd.com> Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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JinZe.Xu authored
[How] Use dc_is_hdmi_signal to determine signal type. Signed-off-by:
JinZe.Xu <JinZe.Xu@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
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