- 01 Feb, 2023 9 commits
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Jisheng Zhang authored
Instead of using absolute addresses for both the old instrucions and the alternative instructions, use offsets relative to the alt_entry values. So this not only cuts the size of the alternative entry, but also meets the prerequisite for patching alternatives in the vDSO, since absolute alternative entries are subject to dynamic relocation, which is incompatible with the vDSO building. Signed-off-by:
Jisheng Zhang <jszhang@kernel.org> Reviewed-by:
Andrew Jones <ajones@ventanamicro.com> Reviewed-by:
Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230128172856.3814-10-jszhang@kernel.orgSigned-off-by:
Palmer Dabbelt <palmer@rivosinc.com>
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Andrew Jones authored
To prepare for 16-bit relocation types to be emitted in alternatives add support for ADD16 and SUB16. Signed-off-by:
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Jisheng Zhang authored
Move find_section() to module.h so that the implementation can be shared by the alternatives code. This will allow us to use alternatives in the vdso. Reviewed-by:
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Jisheng Zhang authored
Switch has_fpu() from static branch to the new helper riscv_has_extension_likely(). Signed-off-by:
Heiko Stuebner <heiko@sntech.de> Reviewed-by:
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Jisheng Zhang authored
Generally, riscv ISA extensions are fixed for any specific hardware platform, so a hart's features won't change after booting. This chacteristic makes it straightforward to use a static branch to check if a specific ISA extension is supported or not to optimize performance. However, some ISA extensions such as SVPBMT and ZICBOM are handled via. the alternative sequences. Basically, for ease of maintenance, we prefer to use static branches in C code, but recently, Samuel found that the static branch usage in cpu_relax() breaks building with CONFIG_CC_OPTIMIZE_FOR_SIZE[1]. As Samuel pointed out, "Having a static branch in cpu_relax() is problematic because that function is widely inlined, including in some quite complex functions like in the VDSO. A quick measurement shows this static branch is responsible by itself for around 40% of the jump table." Samuel's findings pointed out one of a few downsides of static branches usage in C code to handle ISA extensions detected at boot time: static branch's metadata in the __jump_table section, which is not discarded after ISA extensions are finalized, wastes some space. I want to try to solve the issue for all possible dynamic handling of ISA extensions at boot time. Inspired by Mark[2], this patch introduces riscv_has_extension_*() helpers, which work like static branches but are patched using alternatives, thus the metadata can be freed after patching. Link: https://lore.kernel.org/linux-riscv/20220922060958.44203-1-samuel@sholland.org/ [1] Link: https://lore.kernel.org/linux-arm-kernel/20220912162210.3626215-8-mark.rutland@arm.com/ [2] Signed-off-by:
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Jisheng Zhang authored
riscv_cpufeature_patch_func() currently only scans a limited set of cpufeatures, explicitly defined with macros. Extend it to probe for all ISA extensions. Signed-off-by:
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Jisheng Zhang authored
So that ISA extensions can be used in assembly files, convert the multi-letter RISC-V ISA extension IDs enums to macros. In order to make them visible, move the #ifndef __ASSEMBLY__ guard to a later point in the header Signed-off-by:
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Jisheng Zhang authored
Currently riscv_cpufeature_patch_func() does nothing at the RISCV_ALTERNATIVES_EARLY_BOOT stage. Add a check to detect whether we are in this stage and exit early. This will allow us to use riscv_cpufeature_patch_func() for scanning of all ISA extensions. Signed-off-by:
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Jisheng Zhang authored
It's a bit weird to call riscv_noncoherent_supported() each time when insmoding a module. Move the calling out of feature patch func. Signed-off-by:
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- 25 Jan, 2023 4 commits
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Heiko Stuebner authored
Commit b0f4c74e ("RISC-V: Fix unannoted hardirqs-on in return to userspace slow-path") renamed the do_notify_resume function to do_work_pending but did not change the prototype in signal.h Do that now, as the original function does not exist anymore. Fixes: b0f4c74e ("RISC-V: Fix unannoted hardirqs-on in return to userspace slow-path") Signed-off-by:
Heiko Stuebner <heiko.stuebner@vrull.eu> Reviewed-by:
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Jisheng Zhang authored
Alternatives live in a different section, so offsets used by jal instruction will point to wrong locations after the patch got applied. Similar to arm64, adjust the location to consider that offset. Co-developed-by:
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Geert Uytterhoeven authored
Remove trailing whitespace that hurts my eyes. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
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Guo Ren authored
KERN_VIRT_SIZE is 1/4 of the entries of the page global directory, not half. Fixes: f7ae0233 ("riscv: Move KASAN mapping next to the kernel mapping") Signed-off-by:
Guo Ren <guoren@linux.alibaba.com> Signed-off-by:
Guo Ren <guoren@kernel.org> Cc: Alexandre Ghiti <alexandre.ghiti@canonical.com> Reviewed-by:
Alexandre Ghiti <alexghiti@rivosinc.com> Link: https://lore.kernel.org/r/20230110080419.931185-1-guoren@kernel.orgSigned-off-by:
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- 20 Jan, 2023 1 commit
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Palmer Dabbelt authored
This cleans up the ISA string handling to more closely match a version of the ISA spec. This is visible in /proc/cpuinfo and the ordering changes may break something in userspace, but these orderings have changed before without issues so with any luck that's still the case. This also adds documentation so userspace has a better idea of what is intended when it comes to compatibility for /proc/cpuinfo, which should help everyone as this will likely keep changing. * b4-shazam-merge: Documentation: riscv: add a section about ISA string ordering in /proc/cpuinfo RISC-V: resort all extensions in consistent orders RISC-V: clarify ISA string ordering rules in cpu.c Link: https://lore.kernel.org/r/20221205144525.2148448-1-conor.dooley@microchip.comSigned-off-by:
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- 18 Jan, 2023 5 commits
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Conor Dooley authored
The RISC-V specs are permissive in what they allow as the ISA string, but how we output this to userspace in /proc/cpuinfo is quasi uABI. Formalise this as part of the uABI, by documenting the list of rules we use at this point in time. Signed-off-by:
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Conor Dooley authored
Ordering between each and every list of extensions is wildly inconsistent. Per discussion on the lists pick the following policy: - The array defining order in /proc/cpuinfo follows a narrow interpretation of the ISA specifications, described in a comment immediately presiding it. - All other lists of extensions are sorted alphabetically. This will hopefully allow for easier review & future additions, and reduce conflicts between patchsets as the number of extensions grows. Link: https://lore.kernel.org/all/20221129144742.2935581-2-conor.dooley@microchip.com/Suggested-by:
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Conor Dooley authored
While the current list of rules may have been accurate when created it now lacks some clarity in the face of isa-manual updates. Instead of trying to continuously align this rule-set with the one in the specifications, change the role of this comment. This particular comment is important, as the array it "decorates" defines the order in which the ISA string appears to userspace in /proc/cpuinfo. Re-jig and strengthen the wording to provide contributors with a set order in which to add entries & note why this particular struct needs more attention than others. While in the area, add some whitespace and tweak some wording for readability's sake. Suggested-by:
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Palmer Dabbelt authored
This fixes an issue with the K210 Kconfig cleanups, I'm just merging it from that to avoid crossing the streams. * b4-shazam-merge: RISC-V: fix incorrect type of ARCH_CANAAN_K210_DTB_SOURCE Link: https://lore.kernel.org/r/20230111104848.2088516-1-conor.dooley@microchip.comSigned-off-by:
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Conor Dooley authored
When adding the ARCH_ symbol for the builtin K210 dtb, I erroneously used the bool type for something that is quite obviously a string. Unfortunately, there is no such thing as "def_string", but in this case we can use "default" to propagate the value of SOC_CANAAN_K210_DTB_SOURCE to ARCH_CANAAN_K210_DTB_SOURCE. ARCH_CANAAN_K210_DTB_SOURCE is not user selectable, so using olddefconfig etc will update ARCH_CANAAN_K210_DTB_SOURCE to reflect any changes made to SOC_CANAAN_K210_DTB_SOURCE. Fixes: fc432119 ("RISC-V: kconfig.socs: convert usage of SOC_CANAAN to ARCH_CANAAN") Reported-by:
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- 29 Dec, 2022 13 commits
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Palmer Dabbelt authored
Heiko Stuebner <heiko@sntech.de> says: From: Heiko Stuebner <heiko.stuebner@vrull.eu> This series is split out of my work on optimizing string functions and provides the basics to: - actually allowing calls in alternatives Function calls use auipc + jalr to reach those 32bit relative addresses but when they're compiled the offset will be wrong as alternatives live in a different section. So when the patch gets applied the address will point to the wrong location. So similar to arm64 the target addresses need to be updated. This is probably also helpful for other things needing more complex code in alternatives. For v2 I got into some sort of cleanup spree for the general instruction parsing that already existed. A number of places do their own instruction parsing and I tried consolidating some of them. Noteable, the kvm parts still do, but I had to stop somewhere :-) * b4-shazam-merge: RISC-V: fix auipc-jalr addresses in patched alternatives RISC-V: add helpers for handling immediates in U-type and I-type pairs RISC-V: add rd reg parsing to insn.h header RISC-V: add U-type imm parsing to insn.h header RISC-V: kprobes: use central defined funct3 constants RISC-V: rename parse_asm.h to insn.h RISC-V: Move riscv_insn_is_* macros into a common header RISC-V: add auipc elements to parse_asm header RISC-V: add ebreak instructions to definitions RISC-V: detach funct-values from their offset RISC-V: add prefix to all constants/macros in parse_asm.h RISC-V: fix funct4 definition for c.jalr in parse_asm.h Link: https://lore.kernel.org/r/20221223221332.4127602-1-heiko@sntech.deSigned-off-by:
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Heiko Stuebner authored
Alternatives live in a different section, so addresses used by call functions will point to wrong locations after the patch got applied. Similar to arm64, adjust the location to consider that offset. Reviewed-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Tested-by:
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Heiko Stuebner authored
Used together U-type and I-type instructions can for example be used to generate bigger jumps (i.e. in auipc+jalr pairs) by splitting the value into an upper immediate (i.e. auipc) and a 12bit immediate (i.e. jalr). Due to both immediates being considered signed this creates some corner cases, so add some helper to prevent this from getting duplicated in different places. Reviewed-by:
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Heiko Stuebner authored
Add a macro to allow parsing of the rd register from an instruction. Reviewed-by:
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Heiko Stuebner authored
Similar to other existing types, allow extracting the immediate for a U-type instruction. U-type immediates are special in that regard, that the value in the instruction in bits [31:12] already represents the same bits of the immediate, so no shifting is required. U-type immediates are for example used in the auipc instruction, so these constants make it easier to parse such instructions. Reviewed-by:
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Heiko Stuebner authored
Don't redefine values that are already available in the central header asm/insn.h . Use the values from there instead. Reviewed-by:
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Heiko Stuebner authored
The current parse_asm header should become a more centralized place for everything concerning parsing and constructing instructions. We already have a header insn-def.h similar to aarch64, so rename parse_asm.h to insn.h (again similar to aarch64) to show that it's meant for more than simple instruction parsing. Reviewed-by:
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Heiko Stuebner authored
Right now the riscv kernel has (at least) two independent sets of functions to check if an encoded instruction is of a specific type. One in kgdb and one kprobes simulate-insn code. More parts of the kernel will probably need this in the future, so instead of allowing this duplication to go on further, move macros that do the function declaration in a common header, similar to at least aarch64. Reviewed-by:
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Heiko Stuebner authored
Instruction parsing should not be done in individual code, but instead supported by central Right now kgdb and kprobes parse instructions and at least kprobes (and the upcoming auipc+jalr alternative fixer-function) need the auipc instruction. Reviewed-by:
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Heiko Stuebner authored
kprobes need to match ebreak instructions, so add the necessary data to enable us to centralize that functionality. Reviewed-by:
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Heiko Stuebner authored
Rather than defining funct3, funct4, etc values pre-shifted to their target-position in an instruction, define the values themselves and only shift them where needed. This allows using these funct-values in other places as well, for example when decoding functions. At the same time also reduces the use of magic numbers, one would need a spec manual to understand. Reviewed-by:
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Heiko Stuebner authored
Some of the constants and macros already have suitable RV_, RVG_ or RVC_ prefixes. Extend this to the rest of the file as well, as we want to use these things in a broader scope soon. Reviewed-by:
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Heiko Stuebner authored
The opcode definition for c.jalr is c.jalr c_rs1_n0 1..0=2 15..13=4 12=1 6..2=0 This means funct4 consisting of bit [15:12] is 1001b, so the value is 0x9. Fixes: edde5584 ("riscv: Add SW single-step support for KDB") Reported-by:
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- 28 Dec, 2022 1 commit
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Palmer Dabbelt authored
Merge tag 'soc2arch-immutable' of git://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into for-next SOC_FOO to ARCH_FOO conversion for RISC-V RISC-V is an outlier in using SOC_FOO rather than ARCH_FOO for vendors/micro-archs. SOC_FOO may make more sense (I personally prefer it), but the rest of the "world" uses ARCH_FOO. That'd be fine, with with an increasing number of existing SoC vendors moving to RISC-V, unifying our symbol names with the expectations of the rest of the world makes sense. Folks did not seem keen on changing the world (and they can't really be blamed for that) so convert RISC-V over to match. Add some ARCH_FOO stubs alongside the existing SOC_FOO ones, which will be removed once all users of SOC_FOO have been converted*, and convert the DT bits of RISC-V kbuild over to the new symbols. * It may be best to wait until after the next LTS to remove the SOC_FOO ones, for the sake of external users. * tag 'soc2arch-immutable' of git://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: RISC-V: stop directly selecting drivers for SOC_CANAAN RISC-V: stop selecting SiFive clock and serial drivers directly RISC-V: stop selecting the PolarFire SoC clock driver RISC-V: kbuild: convert all use of SOC_FOO to ARCH_FOO RISC-V: kconfig.socs: convert usage of SOC_CANAAN to ARCH_CANAAN RISC-V: introduce ARCH_FOO kconfig aliases for SOC_FOO symbols Signed-off-by:
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- 27 Dec, 2022 6 commits
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Conor Dooley authored
While we cannot yet drop the SOC_ prefixed symbols, we can convert uses of these symbols within Kconfig.socs to the ARCH_ variants. Signed-off-by: -
Conor Dooley authored
The serial and clock drivers will be enabled by default if the symbol itself is enabled, so stop directly selecting the drivers in Kconfigs.socs. Signed-off-by: -
Conor Dooley authored
To facilitate a transfer from SOC_FOO to ARCH_FOO, over a release cycle, introduce some aliases so that drivers etc that use the SOC_FOO symbols can be converted. Signed-off-by: -
Conor Dooley authored
The SiFive clock and serial drivers will now default to the value of SOC_SIFIVE so there is no need to directly select their symbols anymore. Signed-off-by: -
Conor Dooley authored
The driver is now enabled by default if SOC_MICROCHIP_POLARFIRE so there is no longer a need to select it in Kconfig.socs Signed-off-by: -
Conor Dooley authored
Convert all non user visible use of SOC_FOO symbols to their ARCH_FOO variants. The canaan DTs are an outlier in that they're gated at the directory and the file level. Drop the directory level gating while we are swapping the symbol names over. Signed-off-by:
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- 25 Dec, 2022 1 commit
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Linus Torvalds authored
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