1. 18 Jun, 2009 9 commits
  2. 16 Jun, 2009 27 commits
  3. 11 Jun, 2009 4 commits
    • Mats Erik Andersson's avatar
      PCI: expose SMBus on Asus notebook A6L · 4096ed0f
      Mats Erik Andersson authored
      Addition of one unknown subsystem identifier to the quirks handler for
      chipset i82855GM_HB on notebook Asus A6L. This exposes the otherwise
      hidden SMBus controller within the south bridge ICH4-M.
      Signed-off-by: default avatarMats Erik Andersson <mats.andersson@gisladisker.se>
      Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
      4096ed0f
    • Andrew Patterson's avatar
      PCI: Add support for turning PCIe ECRC on or off · 43c16408
      Andrew Patterson authored
      Adds support for PCI Express transaction layer end-to-end CRC checking
      (ECRC).  This patch will enable/disable ECRC checking by setting/clearing
      the ECRC Check Enable and/or ECRC Generation Enable bits for devices that
      support ECRC.
      
      The ECRC setting is controlled by the "pci=ecrc=<policy>" command-line
      option. If this option is not set or is set to 'bios", the enable and
      generation bits are left in whatever state that firmware/BIOS set them to.
      The "off" setting turns them off, and the "on" option turns them on (if the
      device supports it).
      
      Turning ECRC on or off can be a data integrity versus performance
      tradeoff.  In theory, turning it on will catch more data errors, turning
      it off means possibly better performance since CRC does not need to be
      calculated by the PCIe hardware and packet sizes are reduced.
      Signed-off-by: default avatarAndrew Patterson <andrew.patterson@hp.com>
      Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
      43c16408
    • Rafael J. Wysocki's avatar
      PCI PM: Follow PCI_PM_CTRL_NO_SOFT_RESET during transitions from D3 · f62795f1
      Rafael J. Wysocki authored
      According to the PCI PM specification (PCI Bus Power Management
      Interface Specification, Rev. 1.2, Section 5.4.1) we are supposed to
      reinitialize devices that have PCI_PM_CTRL_NO_SOFT_RESET clear during
      all transitions from PCI_D3hot to PCI_D0, but we only do it if the
      device's current_state field is equal to PCI_UNKNOWN.
      
      This may lead to problems if a device with PCI_PM_CTRL_NO_SOFT_RESET
      unset is put into PCI_D3hot at run time by its driver and
      pci_set_power_state() is used to put it back into PCI_D0, because in
      that case the device will remain uninitialized after
      pci_set_power_state() has returned.  Prevent that from happening by
      modifying pci_raw_set_power_state() to reinitialize devices with
      PCI_PM_CTRL_NO_SOFT_RESET unset during all transitions from D3 to D0.
      
      Cc: stable@kernel.org
      Signed-off-by: default avatarRafael J. Wysocki <rjw@sisk.pl>
      Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
      f62795f1
    • Yu Zhao's avatar
      PCI: fix SR-IOV function dependency link problem · 4d135dbe
      Yu Zhao authored
      PCIe root complex integrated endpoint does not implement ARI, so this
      kind of endpoint uses 3-bit function number. The function dependency
      link of the integrated endpoint should be calculated using the device
      number plus the value from function dependency link register.
      
      Normal endpoint always implements ARI and the function dependency link
      register contains 8-bit function number (i.e. `devfn' from software's
      perspective).
      Signed-off-by: default avatarYu Zhao <yu.zhao@intel.com>
      Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
      4d135dbe