These are used by various IP modules.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

This header defines the gfx v9 MEC structures.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

These are the Video Compression Engine registers for vega10.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

These are the Unifed Video Decoder registers for vega10.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

These are the THerMal control registers for vega10.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

These are the System Managment Unit IO registers for vega10.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

These are the System DMA register headers for vega10.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

These are the OS Services register headers for vega10.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

These are the Bus IO registers for vega10.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

These are the Bus InterFace registers for vega10.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

MP is the system management controller on vega10.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Add the MultiMedia Hub registers for vega10.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

These are the Host Data Path registers for vega10.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Add the Graphics Core register headers for vega10.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

These are the register headers for the Display
and Composition Engine on vega10.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

ATHUB is part of the memory controller on soc15 asics.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

This adds the register bitfield enums for vega10.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

This header defines the IP layout for soc15 based SoCs.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

This adds basic support for asics that use atomfirmware.h
to define their vbios tables.

v2: rebase
v3: squash in num scratch reg fix
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

There will be a slightly different version for atomfirmware.
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Supposedly atomfirmware rom header is 3.3 atombios is 1.1.

v2: rebased on newer kernel
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

soc15 asics have a new vbios interface.  These headers
define that interface.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

We will add the fence to freed buffer objects in a later commit, to ensure
that the underlying memory can only be re-used after all references in
page tables have been cleared.
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Power containment will degrade performance in some compute tests.
Restore disabling it as before code refining in powerplay.

v2: only in the compute profile
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

The ring structure already has what we need.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Avoids passing around additional parameters during setup.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Everything we need is in the ring structure.  No need to
pass all the bits explicitly.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

It's required.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

No need to loop through the compute queues twice.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

If KIQ isn't working, the compute rings won't work either.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

It's required.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

To better match where they are used.  Called from sw_init
and sw_fini.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

load mc ucode in driver if VBIOS not loaded
a full version of MC ucode,
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: jimqu <Jim.Qu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

it could come from branch merge.
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

the ixcurrent_pg_status addr is different between APU and DGPU.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Samuel Li <Samuel.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>