- 28 Jun, 2018 2 commits
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Joe Perches authored
random_ether_addr is a #define for eth_random_addr which is generally preferred in kernel code by ~3:1 Convert the uses of random_ether_addr to enable removing the #define Signed-off-by:
Joe Perches <joe@perches.com> Signed-off-by:
Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/19600/ Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@linux-mips.org
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Paul Burton authored
Annotate cpu_wait implementations using the __cpuidle macro which places these functions in the .cpuidle.text section. This allows cpu_in_idle() to return true for PC values which fall within these functions, allowing nmi_backtrace() to produce cleaner output for CPUs running idle functions. For example: # echo l >/proc/sysrq-trigger [ 38.587170] sysrq: SysRq : Show backtrace of all active CPUs [ 38.593657] NMI backtrace for cpu 1 [ 38.597611] CPU: 1 PID: 161 Comm: sh Not tainted 4.18.0-rc1+ #27 [ 38.604306] Stack : 00000000 00000004 00000006 80486724 00000000 00000000 00000000 00000000 [ 38.613647] 80e17eda 00000034 00000000 00000000 80d20000 80b67e98 8e559c90 0ffe1e88 [ 38.622986] 00000000 00000000 80e70000 00000000 8f61db18 38312e34 722d302e 202b3163 [ 38.632324] 8e559d3c 8e559adc 00000001 6b636162 80d20000 80000000 00000000 80d1cfa4 [ 38.641664] 00000001 80d20000 80d19520 00000000 00000003 80836724 00000004 80e10004 [ 38.650993] ... [ 38.653724] Call Trace: [ 38.656499] [<8040cdd0>] show_stack+0xa0/0x144 [ 38.661475] [<80b67e98>] dump_stack+0xe8/0x120 [ 38.666455] [<80b6f6d4>] nmi_cpu_backtrace+0x1b4/0x1cc [ 38.672189] [<80b6f81c>] nmi_trigger_cpumask_backtrace+0x130/0x1e4 [ 38.679081] [<808295d8>] __handle_sysrq+0xc0/0x180 [ 38.684421] [<80829b84>] write_sysrq_trigger+0x50/0x64 [ 38.690176] [<8061c984>] proc_reg_write+0xd0/0xfc [ 38.695447] [<805aac1c>] __vfs_write+0x54/0x194 [ 38.700500] [<805aaf24>] vfs_write+0xe0/0x18c [ 38.705360] [<805ab190>] ksys_write+0x7c/0xf0 [ 38.710238] [<80416018>] syscall_common+0x34/0x58 [ 38.715558] Sending NMI from CPU 1 to CPUs 0,2-3: [ 38.720916] NMI backtrace for cpu 0 skipped: idling at r4k_wait_irqoff+0x2c/0x34 [ 38.729186] NMI backtrace for cpu 3 skipped: idling at r4k_wait_irqoff+0x2c/0x34 [ 38.737449] NMI backtrace for cpu 2 skipped: idling at r4k_wait_irqoff+0x2c/0x34 Without this we get register value & backtrace output from all CPUs, which is generally useless for those running the idle function & serves only to overwhelm & obfuscate the meaningful output from non-idle CPUs. Signed-off-by:
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- 24 Jun, 2018 38 commits
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Rickard Strandqvist authored
Remove the function sb1_dma_init() that is not used anywhere. This was partially found by using a static code analysis program called cppcheck. Signed-off-by:
Rickard Strandqvist <rickard_strandqvist@spectrumdigital.se> Patchwork: https://patchwork.linux-mips.org/patch/8873/Signed-off-by:
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Rickard Strandqvist authored
Remove the function pci_enable_swapping() that is not used anywhere. This was partially found by using a static code analysis program called cppcheck. Signed-off-by:
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Paul Burton authored
Remove the platform code used to power down the system, instead relying upon the new PIIX4 poweroff driver. This reduces the amount of platform code required for the Malta board in preparation for allowing it to be part of a more generic kernel. Signed-off-by:
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Paul Burton authored
DMA coherence is not user-selectable in Kconfig, and Malta selects CONFIG_DMA_MAYBE_COHERENT which in turn selects CONFIG_DMA_NONCOHERENT. Remove #ifdefs whose conditions can therefore never be true for Malta. This removes a significant amount of code from bonito_quirks_setup(), but the code is duplicated in plat_enable_iocoherency() anyway so we lose nothing but duplication. Signed-off-by:
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Paul Burton authored
In systems that include a MIPS Coherency Manager, the icache always fills from a cache which is coherent across all CPUs. In I6400 & I6500 systems the icache fills from the dcache which is coherent across all CPUs. In all other CM-based systems the icache fills from the L2 cache which is shared between all cores. This means that an icache will always see stores from remote CPUs without needing to write them back any further than that L2, which is what the cpu_icache_snoops_remote_store feature is used to test. In order for it to return 1 without needing a per-platform override (which is what Malta has relied upon so far) set the MIPS_IC_SNOOPS_REMOTE flag when a CM is present. Signed-off-by:
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Joshua Kinard authored
This is a manual cherrypick of commit c7ddc3d137b7 from Alastair Bridgewater's IP35 tree that replaces two cases of "if (bus->number > 0)" with a more correct "if (!pci_is_root_bus(bus))" in arch/mips/pci/ops-bridge.c. Cc: linux-mips@linux-mips.org Cc: Alastair Bridgewater <alastair.bridgewater@gmail.com> Suggested-by:
Alastair Bridgewater <alastair.bridgewater@gmail.com> Signed-off-by:
Joshua Kinard <kumba@gentoo.org> Patchwork: https://patchwork.linux-mips.org/patch/17501/Signed-off-by:
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Paul Burton authored
Commit 6b832257 ("MIPS: Force CPUs to lose FP context during mode switches") ensures that we react to PR_SET_FP_MODE prctl syscalls quickly by broadcasting an IPI in order to cause CPUs to lose FPU access when necessary. Whilst it achieves that, unfortunately it causes all sorts of strange race conditions because: 1) The IPI may arrive at a point where the FPU is in the process of being enabled, but that process is not yet complete leading to a state we aren't prepared to handle. For example: [ 370.215903] do_cpu invoked from kernel context![#1]: [ 370.221064] CPU: 0 PID: 963 Comm: fp-prctl Not tainted 4.9.0-rc5-00323-g210db32-dirty #226 [ 370.229420] task: a8000000fd672e00 task.stack: a8000000fd630000 [ 370.235399] $ 0 : 0000000000000000 0000000000000001 0000000000000001 a8000000fd630000 [ 370.243882] $ 4 : a8000000fd672e00 0000000000000000 0000000000000453 0000000000000000 [ 370.252317] $ 8 : 0000000000000000 a8000000fd637c28 1000000000000000 0000000000000010 [ 370.260753] $12 : 00000000140084e0 ffffffff80109c00 0000000000000000 0000000000000002 [ 370.269179] $16 : ffffffff8092f080 a8000000fd672e00 ffffffff80107fe8 a8000000fd485000 [ 370.277612] $20 : ffffffff8084d328 ffffffff80940000 0000000000000009 ffffffff80930000 [ 370.286038] $24 : 0000000000000000 900000001612048c [ 370.294476] $28 : a8000000fd630000 a8000000fd637ac0 ffffffff80937300 ffffffff8010807c [ 370.302909] Hi : 0000000000000000 [ 370.306595] Lo : 0000000000000200 [ 370.310376] epc : ffffffff80115d38 _save_fp+0x10/0xa0 [ 370.315784] ra : ffffffff8010807c prepare_for_fp_mode_switch+0x94/0x1b0 [ 370.322707] Status: 140084e2 KX SX UX KERNEL EXL [ 370.327980] Cause : 1080002c (ExcCode 0b) [ 370.332091] PrId : 0001a428 (MIPS P6600) [ 370.336179] Modules linked in: [ 370.339486] Process fp-prctl (pid: 963, threadinfo=a8000000fd630000, task=a8000000fd672e00, tls=00000000756e67d0) [ 370.349724] Stack : 0000000000000000 a8000000fd557dc0 0000000000000000 ffffffff801ca8e0 [ 370.358161] 0000000000000000 a8000000fd637b9c 0000000000000009 ffffffff80923780 [ 370.366575] ffffffff80850000 ffffffff8011610c 00000000000000b8 ffffffff801a5084 [ 370.374989] ffffffff8084a370 ffffffff8084a388 ffffffff80923780 ffffffff80923828 [ 370.383395] 0000000000010000 ffffffff809237a8 0000000000020000 ffffffff80a40000 [ 370.391817] 000000000000007c 00000000004a0000 00000000756dedd0 ffffffff801a5188 [ 370.400230] a800000002014900 0000000000000001 ffffffff80923780 0000000080923828 [ 370.408644] ffffffff80923780 ffffffff80923780 ffffffff80923828 ffffffff801a521c [ 370.417066] ffffffff80923780 ffffffff80923828 0000000000010000 ffffffff801a8f84 [ 370.425472] ffffffff80a40000 a8000000fd637c20 ffffffff80a39240 0000000000000001 [ 370.433885] ... [ 370.436562] Call Trace: [ 370.439222] [<ffffffff80115d38>] _save_fp+0x10/0xa0 [ 370.444305] [<ffffffff8010807c>] prepare_for_fp_mode_switch+0x94/0x1b0 [ 370.451035] [<ffffffff801ca8e0>] flush_smp_call_function_queue+0xf8/0x230 [ 370.457991] [<ffffffff8011610c>] ipi_call_interrupt+0xc/0x20 [ 370.463814] [<ffffffff801a5084>] __handle_irq_event_percpu+0xc4/0x1a8 [ 370.470404] [<ffffffff801a5188>] handle_irq_event_percpu+0x20/0x68 [ 370.476734] [<ffffffff801a521c>] handle_irq_event+0x4c/0x88 [ 370.482486] [<ffffffff801a8f84>] handle_edge_irq+0x12c/0x210 [ 370.488316] [<ffffffff801a47a0>] generic_handle_irq+0x38/0x48 [ 370.494280] [<ffffffff804a2dbc>] gic_handle_shared_int+0x194/0x268 [ 370.500616] [<ffffffff801a47a0>] generic_handle_irq+0x38/0x48 [ 370.506529] [<ffffffff80107e60>] do_IRQ+0x18/0x28 [ 370.511445] [<ffffffff804a1524>] plat_irq_dispatch+0xc4/0x140 [ 370.517339] [<ffffffff80106230>] ret_from_irq+0x0/0x4 [ 370.522583] [<ffffffff8010fad4>] do_ri+0x4fc/0x7e8 [ 370.527546] [<ffffffff80106220>] ret_from_exception+0x0/0x10 2) The IPI may arrive during kernel use of the FPU, since we generally only disable preemption around use of the FPU & leave interrupts enabled. This can lead to us unexpectedly losing access to the FPU in places where it previously had not been possible. For example: do_cpu invoked from kernel context![#2]: CPU: 2 PID: 7338 Comm: fp-prctl Tainted: G D 4.7.0-00424-g49b0c82 #2 task: 838e4000 ti: 88d38000 task.ti: 88d38000 $ 0 : 00000000 00000001 ffffffff 88d3fef8 $ 4 : 838e4000 88d38004 00000000 00000001 $ 8 : 3400fc01 801f8020 808e9100 24000000 $12 : dbffffff 807b69d8 807b0000 00000000 $16 : 00000000 80786150 00400fc4 809c0398 $20 : 809c0338 0040273c 88d3ff28 808e9d30 $24 : 808e9d30 00400fb4 $28 : 88d38000 88d3fe88 00000000 8011a2ac Hi : 0040273c Lo : 88d3ff28 epc : 80114178 _restore_fp+0x10/0xa0 ra : 8011a2ac mipsr2_decoder+0xd5c/0x1660 Status: 1400fc03 KERNEL EXL IE Cause : 1080002c (ExcCode 0b) PrId : 0001a920 (MIPS I6400) Modules linked in: Process fp-prctl (pid: 7338, threadinfo=88d38000, task=838e4000, tls=766527d0) Stack : 00000000 00000000 00000000 88d3fe98 00000000 00000000 809c0398 809c0338 808e9100 00000000 88d3ff28 00400fc4 00400fc4 0040273c 7fb69e18 004a0000 004a0000 004a0000 7664add0 8010de18 00000000 00000000 88d3fef8 88d3ff28 808e9100 00000000 766527d0 8010e534 000c0000 85755000 8181d580 00000000 00000000 00000000 004a0000 00000000 766527d0 7fb69e18 004a0000 80105c20 ... Call Trace: [<80114178>] _restore_fp+0x10/0xa0 [<8011a2ac>] mipsr2_decoder+0xd5c/0x1660 [<8010de18>] do_ri+0x90/0x6b8 [<80105c20>] ret_from_exception+0x0/0x10 At first glance a simple fix may seem to be to disable interrupts around kernel use of the FPU rather than merely preemption, however this would introduce further overhead outside of the mode switch path & doesn't solve the third problem: 3) The IPI may arrive whilst the kernel is running code that will lead to a preempt_disable() call & FPU usage soon. If this happens then the IPI will be serviced & we'll proceed to enable an FPU whilst the mode switch is in progress, leading to strange & inconsistent behaviour. Further to all of this is a separate but related problem: 4) There are various paths through which we may enable the FPU without the user having triggered a coprocessor 1 disabled exception. These paths are those in which we emulate instructions & then enable the FPU with the expectation that the user might execute an FP instruction shortly afterwards. However these paths have not previously checked whether an FP mode switch is underway for the task, and therefore could enable the FPU whilst such a mode switch is in progress leading to strange & inconsistent behaviour for user code. This patch fixes all of the above by taking a step back & re-examining our approach to FP mode switches. Up until now we have taken these basic steps: a) Prevent any threads that are part of the affected process from being able to obtain ownership of the FPU. b) Cause any threads that are part of the affected process and already have ownership of an FPU to lose it. c) Set the thread flags for each thread that is part of the affected process to reflect the new FP mode. d) Allow threads to obtain ownership of the FPU again. This approach is however more complex than necessary. All that we really require is that the mode switch has occurred for all threads that are part of the affected process before mips_set_process_fp_mode(), and thus the PR_SET_FP_MODE prctl() syscall, returns. This doesn't require that we stop threads from owning or using an FPU whilst a mode switch occurs, only that we force them to relinquish it after the mode switch has occurred such that they next own an FPU with the correct mode configured. Our basic steps therefore simplify to: A) Set the thread flags for each thread that is part of the affected process to reflect the new FP mode. B) Cause any threads that are part of the affected process and already have ownership of an FPU to lose it. We implement B) by forcing each CPU which might be running a thread which is part of the affected process to schedule a no-op function, which causes the affected thread to lose its FPU ownership when it is descheduled. The end result is simpler FP mode switching with less overhead in the FPU enable path (ie. enable_restore_fp_context()) and fewer moving parts. Signed-off-by:
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Rob Herring authored
The DT core will call of_platform_default_populate, so it is not necessary for arch specific code to call it unless there are custom match entries, auxdata or parent device. Neither of those apply here, so remove the call. Cc: John Crispin <john@phrozen.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Paul Burton <paul.burton@mips.com> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@linux-mips.org Signed-off-by:
Rob Herring <robh@kernel.org> Patchwork: https://patchwork.linux-mips.org/patch/19592/Signed-off-by:
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Rob Herring authored
The DT core will call of_platform_populate, so it is not necessary for arch specific code to call it unless there are custom match entries, auxdata or parent device. Neither of those apply here, so remove the call. Cc: Paul Burton <paul.burton@mips.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@linux-mips.org Signed-off-by:
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Rob Herring authored
The DT core will register "simple-bus" by default, so it is not necessary for arch specific code to do so unless there are custom match entries, auxdata or parent device. Neither of those apply here, so remove the call. Cc: Kevin Cernekee <cernekee@gmail.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Paul Burton <paul.burton@mips.com> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@linux-mips.org Signed-off-by:
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Rob Herring authored
The DT core code will probe "simple-bus" by default, so remove the Netlogic specific call. The probing of simple-bus happens at arch_initcall_sync, so the call being removed here is already a nop. Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Paul Burton <paul.burton@mips.com> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@linux-mips.org Signed-off-by:
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Rob Herring authored
of_platform_bus_probe is deprecated in favor of of_platform_populate. of_platform_populate is stricter requiring compatible properties for matching rather than name or type. Octeon uses compatible strings for matching, so convert it to of_platform_populate. Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Paul Burton <paul.burton@mips.com> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@linux-mips.org Signed-off-by:
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Heiher authored
On SMP systems, the shared ejtag debug buffer may be overwritten by other cores, because every cores can generate ejtag exception at same time. Unfortunately, in that context, it's difficult to relax more registers to access per cpu buffers. so use ll/sc to serialize the access. [paul.burton@mips.com: This could in theory be backported at least as far back as the beginning of the git era, however in general it's exceedingly rare that anyone would hit this without further changes, so it doesn't seem worthwhile marking for backport.] Signed-off-by:
Heiher <r@hev.cc> Patchwork: https://patchwork.linux-mips.org/patch/19507/Signed-off-by:
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Masahiro Yamada authored
Merge the build rule of vmlinux.{gz,bz2,lzma,lzo}.itb, and also move 'targets' close to the related code. [paul.burton@mips.com: - Remove leading tabs from assignments to itb_addr_cells, since after this patch moves the additions to the 'targets' variable the assignments to itb_addr_cells wound up being treated as part of the uImage rule above them, causing the .its to incorrectly be generated with empty ADDR_CELLS.] Signed-off-by:Masahiro Yamada <yamada.masahiro@socionext.com> Patchwork: https://patchwork.linux-mips.org/patch/19095/Signed-off-by:
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Masahiro Yamada authored
The build rule of vmlinux.*.its is invoked by $(call if_changed,...) but it always rebuilds the target needlessly due to missing targets. Signed-off-by:
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Masahiro Yamada authored
As Documentation/kbuild/makefile.txt says, it is a typical mistake to forget the FORCE prerequisite for the rule invoked by if_changed. Add the FORCE to the prerequisite, but it must be filtered-out from the files passed to the 'cat' command. Because this rule generates .vmlinux.its.S.cmd, vmlinux.its.S must be specified as targets so that the .cmd file is included. Signed-off-by:
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Masahiro Yamada authored
$(CPP) is used here to perform macro replacement in ITS. Do not pass $(cpp_flags) because it pulls in more options for dependency file generation etc. but none of which is necessary here. ITS files do not include any header file, so $(call if_change,...) is enough. Signed-off-by:
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Masahiro Yamada authored
This reverts commit 0f9da844. It is true that commit 0f9da844 ("MIPS: boot: Define __ASSEMBLY__ for its.S build") fixed the build error, but it should not have defined __ASSEMBLY__ just for textual substitution in arbitrary data. The file is image tree source in this case, but the purpose of using CPP is to replace some macros. I merged a better solution, commit a95b37e2 ("kbuild: get <linux/compiler_types.h> out of <linux/kconfig.h>"). The original fix-up is no longer needed. Signed-off-by:
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Nicholas Mc Guire authored
Booleans should be assigned true/false not 1/0 as comparison is not needed Signed-off-by:
Nicholas Mc Guire <hofrat@osadl.org> Patchwork: https://patchwork.linux-mips.org/patch/19559/Signed-off-by:
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Christoph Hellwig authored
Keep this file as light as possible as it gets pulled into every driver using dma mapping APIs. Signed-off-by:
Christoph Hellwig <hch@lst.de> Patchwork: https://patchwork.linux-mips.org/patch/19552/Signed-off-by:
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Christoph Hellwig authored
Now unused. Signed-off-by:
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Christoph Hellwig authored
Provide phys_to_dma/dma_to_phys helpers, and the special arch_sync_dma_for_cpu_all hook, everything else is generic Signed-off-by:
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Christoph Hellwig authored
The MIPS bmips platform needs a global flush when transferring ownership back to the CPU. Add a hook for that to the dma-noncoherent implementation. Signed-off-by:
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Christoph Hellwig authored
Jazz actually has a very basic IOMMU, so split the ops into a separate implementation from the generic default support (which is about to go away anyway). Signed-off-by:
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Christoph Hellwig authored
Provide phys_to_dma/dma_to_phys helpers only if PCI support is enabled, everything else is generic. Signed-off-by:
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Christoph Hellwig authored
Provide phys_to_dma/dma_to_phys helpers, everything else is generic. Signed-off-by:
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Christoph Hellwig authored
Provide phys_to_dma/dma_to_phys helpers, everything else is generic. Signed-off-by:
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Christoph Hellwig authored
Convert everything not overriding dma-coherence.h to the generic noncoherent ops. The new dma-noncoherent.c file duplicates a lot of the code in dma-default.c, but that file will be gone by the end of this series. Signed-off-by:
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Christoph Hellwig authored
We want to be able to use it even when not building dma-default.c in the near future. Signed-off-by:
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Christoph Hellwig authored
IP27 is coherent and has a reasonably direct mapping, just with a little per-bus offset added into the dma address. Signed-off-by:
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Christoph Hellwig authored
Switch the simple cache coherent architectures that don't require any DMA address translation to dma_direct_ops. We'll soon use at least parts of the direct DMA ops implementation for all platforms, so select the symbol globally. Signed-off-by:
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Christoph Hellwig authored
Loongson3 is dma coherent and uses swiotlb, so it will never used any of these helpers. Signed-off-by:
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Christoph Hellwig authored
Only loongson-3 is DMA coherent and uses swiotlb. So move the dma address translations stubs directly to the loongson-3 code, and remove a few Kconfig indirections. Signed-off-by:
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Christoph Hellwig authored
No need to pull them into a global header. Signed-off-by:
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Christoph Hellwig authored
Octeon doesn't use the dma-default code, and now doesn't built it either, so these stubs can be removed. Signed-off-by:
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Christoph Hellwig authored
Octeon and loonson64 already don't use it at all, and we're going to migrate more plaforms away from it. Signed-off-by:
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Christoph Hellwig authored
And use mips_default_dma_map_ops directly. Signed-off-by:
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Christoph Hellwig authored
Octeon and Loongson share exactly the same code, move it into a common implementation, and use that implementation directly from get_arch_dma_ops. Also provide the expected dma-direct.h helpers directly instead of delegating to platform dma-coherence.h headers. Signed-off-by:
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