- 11 Jun, 2021 4 commits
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Thierry Reding authored
The secure firmware keeps some SID override registers set as passthrough in order to allow devices such as the display controller to operate with no knowledge of SMMU translations until an operating system driver takes over. This is needed in order to seamlessly transition from the firmware framebuffer to the OS framebuffer. Upon successfully attaching a device to the SMMU and in the process creating identity mappings for memory regions that are being accessed, the Tegra implementation will call into the memory controller driver to program the override SIDs appropriately. Signed-off-by:
Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20210603164632.1000458-6-thierry.reding@gmail.comSigned-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
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Thierry Reding authored
Parse the reg property in device tree and detect the number of instances represented by a device tree node. This is subsequently needed in order to support single-instance SMMUs with the Tegra implementation because additional programming is needed to properly configure the SID override registers in the memory controller. Signed-off-by:
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Thierry Reding authored
The ARM SMMU instantiations found on Tegra186 and later need inter- operation with the memory controller in order to correctly program stream ID overrides. Furthermore, on Tegra194 multiple instances of the SMMU can gang up to achieve higher throughput. In order to do this, they have to be programmed identically so that the memory controller can interleave memory accesses between them. Add the Tegra186 compatible string to make sure the interoperation with the memory controller can be enabled on that SoC generation. Signed-off-by:
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Krzysztof Kozlowski authored
Merge branch 'for-thierry/arm-smmu' of https://git.kernel.org/pub/scm/linux/kernel/git/will/linux into for-v5.14/tegra-mc Pull ARM SMMU driver change from Will Deacon to resolve dependencies between memory controllers, Tegra ARM SoC and ARM SMMU drivers trees. Further ARM SMMU changes for Tegra depend on the change in Will's tree and on Tegra memory controllers drivers work done before by Thierry Reding. Pulling Will's tree allows to apply the rest of this ARM SMMU Tegra work via memory controllers drivers tree. Signed-off-by:
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- 10 Jun, 2021 1 commit
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Dan Carpenter authored
The debugfs_create_dir() function does not return NULL, it returns error pointers. But in normal situations like this where the caller is not dereferencing "emc->debugfs.root" then we are not supposed to check the return. So instead of fixing these checks, we should delete them. Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Link: https://lore.kernel.org/r/YMCQDTSyG8UuQoh0@mwandaSigned-off-by:
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- 08 Jun, 2021 1 commit
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Thierry Reding authored
Implement a ->probe_finalize() callback that can be used by vendor implementations to perform extra programming necessary after devices have been attached to the SMMU. Signed-off-by:
Will Deacon <will@kernel.org>
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- 03 Jun, 2021 17 commits
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Thierry Reding authored
Instead of programming all SID overrides during early boot, perform the operation on-demand after the SMMU translations have been set up for a device. This reuses data from device tree to match memory clients for a device and programs the SID specified in device tree, which corresponds to the SID used for the SMMU context banks for the device. Signed-off-by:
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Thierry Reding authored
Keep the directory structure consistent by splitting the Tegra194 data into a separate file. Signed-off-by:
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Thierry Reding authored
The memory client IDs will subsequently be used to program override SIDs for the given clients depending on the device tree configuration. Signed-off-by:
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Thierry Reding authored
The Tegra210 (and earlier) driver now supports all the functionality that the Tegra186 (and later) driver does, so they can be unified. Note that previously the Tegra186 (and later) driver could be unloaded, even if that was perhaps not very useful. Older chips don't support that yet, but once they do this code can be reenabled. Signed-off-by:
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Thierry Reding authored
The memory controller hot resets are implemented in the BPMP on Tegra186 and later, so there's no need to provide an implementation via the memory controller driver. Conditionally register the reset controller only if needed. Signed-off-by:
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Thierry Reding authored
Make IRQ support optional to help unify the Tegra186 memory controller driver with this one. Signed-off-by:
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Thierry Reding authored
Tegra20 requires a slightly different interrupt handler than Tegra30 and later, so parameterize the handler, so that each SoC implementation can provide its own. Signed-off-by:
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Thierry Reding authored
Separate the setup code for Tegra30 and later into a ->setup() callback and set it for all applicable chips. Signed-off-by:
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Thierry Reding authored
The current per-SoC setup code runs at a fairly arbitrary point during probe, thereby making it less flexible for other SoC generations. Move the call around slightly (after only the very basic, common setup that applies to all SoC generations has been performed), which will allow it to be used for other implementations. Signed-off-by:
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Thierry Reding authored
Continuing the scheme of unification, push suspend/resume callbacks into per-SoC driver so that they can be properly parameterized. Signed-off-by:
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Thierry Reding authored
Subsequent patches will introduce further callbacks, so create a new struct tegra_mc_ops to collect all of them in a single place. Move the existing ->init() callback into the new structure. Signed-off-by:
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Thierry Reding authored
As another step towards unifying both the Tegra210 (and earlier) and Tegra186 (and later) memory controller drivers, unify the structures that are used to represent them. Note that this comes at a slight space penalty since some fields are not used on all generations, but the benefits of unifying the driver outweigh the downsides. Signed-off-by:
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Thierry Reding authored
Subsequent patches will add more register fields to the tegra_mc_client structure, so consolidate all register field definitions into a common sub-structure for coherency. Signed-off-by:
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Krzysztof Kozlowski authored
Merge tag 'tegra-for-5.14-memory' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into for-v5.14/tegra-mc memory: tegra: Changes for v5.14-rc1 This stable tag contains Dmitry's power domain work, including all the necessary dependencies from the regulator, clock and ARM SoC trees. Further work depends on memory controller changes here.
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Dmitry Osipenko authored
Use common devm_tegra_core_dev_init_opp_table() helper for the OPP table initialization. Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30 Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30 Reviewed-by:
Dmitry Osipenko <digetx@gmail.com> Signed-off-by:
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Dmitry Osipenko authored
Use common devm_tegra_core_dev_init_opp_table() helper for the OPP table initialization. Tested-by: Paul Fertser <fercerpav@gmail.com> # PAZ00 T20 Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20 Reviewed-by:
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Dmitry Osipenko authored
Enable compile testing for all Tegra memory drivers. Reviewed-by:
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- 01 Jun, 2021 10 commits
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Dmitry Osipenko authored
Fix compilation warning on 64bit platforms caused by implicit promotion of 32bit signed integer to a 64bit unsigned value which happens after enabling compile-testing of the EMC drivers. Reported-by:
kernel test robot <lkp@intel.com> Reviewed-by:
Nathan Chancellor <nathan@kernel.org> Reviewed-by:
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Thierry Reding authored
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Thierry Reding authored
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Dmitry Osipenko authored
Add stubs needed for compile-testing of Tegra memory drivers. Signed-off-by:
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Dmitry Osipenko authored
Add missing stubs that will allow Tegra memory driver to be compile-tested by kernel build bots. Signed-off-by:
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Dmitry Osipenko authored
Add common helper which initializes OPP table for Tegra SoC core devices. Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30 Tested-by: Paul Fertser <fercerpav@gmail.com> # PAZ00 T20 Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20 and TK1 T124 Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30 Signed-off-by:
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Dmitry Osipenko authored
Add stub required for compile-testing of drivers. Signed-off-by:
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Dmitry Osipenko authored
Ensure that SoC voltages are at a level suitable for a system reboot. This is important for some devices that use CPU reset method for the rebooting. SoC CPU and core voltages now are be restored to a level that is suitable for rebooting. This patch fixes hang on reboot on Asus Transformer TF101, it was also reported as fixing some of reboot issues on Toshiba AC100. Reported-by:
Nikola Milosavljević <mnidza@outlook.com> Tested-by: Nikola Milosavljević <mnidza@outlook.com> # TF101 Signed-off-by:
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Thierry Reding authored
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Dmitry Osipenko authored
Some NVIDIA Tegra devices use a CPU soft-reset method for the reboot and in this case we need to restore the coupled voltages to the state that is suitable for hardware during boot. Add new regulator_sync_voltage_rdev() helper which is needed by regulator drivers in order to sync voltage of a coupled regulators. Acked-by:
Mark Brown <broonie@kernel.org> Signed-off-by:
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- 31 May, 2021 7 commits
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Dmitry Osipenko authored
The Tegra clock driver contains legacy code which deasserts hardware reset when peripheral clocks are enabled. This behaviour comes from a pre-CCF era of the Tegra drivers. This is unacceptable for modern kernel drivers which use generic CCF and reset-control APIs because it breaks assumptions of the drivers about clk/reset sequences and about reset-propagation delays. Hence remove the awkward legacy behaviour from the clk driver. In particular PMC driver assumes that hardware blocks remains in reset while power domain is turning on, but the clk driver deasserts the reset before power clamp is removed, hence breaking the driver's assumption. Signed-off-by:
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Dmitry Osipenko authored
The external clocks don't have reset bits as they don't belong to any specific hardware unit. Mark them as not having reset control for consistency. Signed-off-by:
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Dmitry Osipenko authored
Check whether thermal DIV2 throttle is active in order to report the CPU frequency properly. This very useful for userspace tools like cpufreq-info which show actual frequency asserted from hardware. Signed-off-by:
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Dmitry Osipenko authored
Zero clock rate doesn't make sense for PLLs and tegra-clk driver enters into infinite loop on trying to calculate PLL parameters for zero rate. Make code to error out if requested rate is zero. Originally this trouble was found by Robert Yang while he was trying to bring up upstream kernel on Samsung Galaxy Tab, which happened due to a bug in Tegra DRM driver that erroneously sets PLL rate to zero. This issues came over again recently during of kernel bring up on ASUS TF700T. Signed-off-by:
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Dmitry Osipenko authored
Higher SCLK rates on Tegra20 require high core voltage. The higher clock rate may have a positive performance effect only for AHB DMA transfers and AVP CPU, but both aren't used by upstream kernel at all. Halve SCLK rate on Tegra20 in order to remove the high core voltage requirement. Acked-by:
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Dmitry Osipenko authored
The PLLU (USB) consists of the PLL configuration itself and configuration of the PLLU outputs. The PLLU programming is inconsistent on T30 vs T114, where T114 immediately bails out if PLLU is enabled and T30 re-enables a potentially already enabled PLL (left after bootloader) and then fully reprograms it, which could be unsafe to do. The correct way should be to skip enabling of the PLL if it's already enabled and then apply configuration to the outputs. This patch doesn't fix any known problems, it's a minor improvement. Acked-by:
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Dmitry Osipenko authored
The refcounting of the gate clocks has a bug causing the enable_refcnt to underflow when unused clocks are disabled. This happens because clk provider erroneously bumps the refcount if clock is enabled at a boot time, which it shouldn't be doing, and it does this only for the gate clocks, while peripheral clocks are using the same gate ops and the peripheral clocks are missing the initial bump. Hence the refcount of the peripheral clocks is 0 when unused clocks are disabled and then the counter is decremented further by the gate ops, causing the integer underflow. Fix this problem by removing the erroneous bump and by implementing the disable_unused() callback, which disables the unused gates properly. The visible effect of the bug is such that the unused clocks are never gated if a loaded kernel module grabs the unused clocks and starts to use them. In practice this shouldn't cause any real problems for the drivers and boards supported by the kernel today. Acked-by:
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