- 15 May, 2018 40 commits
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Emily Deng authored
issue: there are VMC page fault occurred if force APP kill during 3dmark test, the cause is in entity_fini we manually signal all those jobs in entity's queue which confuse the sync/dep mechanism: 1)page fault occurred in sdma's clear job which operate on shadow buffer, and shadow buffer's Gart table is cleaned by ttm_bo_release since the fence in its reservation was fake signaled by entity_fini() under the case of SIGKILL received. 2)page fault occurred in gfx' job because during the lifetime of gfx job we manually fake signal all jobs from its entity in entity_fini(), thus the unmapping/clear PTE job depend on those result fence is satisfied and sdma start clearing the PTE and lead to GFX page fault. fix: 1)should at least wait all jobs already scheduled complete in entity_fini() if SIGKILL is the case. 2)if a fence signaled and try to clear some entity's dependency, should set this entity guilty to prevent its job really run since the dependency is fake signaled. v2: splitting drm_sched_entity_fini() into two functions: 1)The first one is does the waiting, removes the entity from the runqueue and returns an error when the process was killed. 2)The second one then goes over the entity, install it as completion signal for the remaining jobs and signals all jobs with an error code. v3: 1)Replace the fini1 and fini2 with better name 2)Call the first part before the VM teardown in amdgpu_driver_postclose_kms() and the second part after the VM teardown 3)Keep the original function drm_sched_entity_fini to refine the code. v4: 1)Rename entity->finished to entity->last_scheduled; 2)Rename drm_sched_entity_fini_job_cb() to drm_sched_entity_kill_jobs_cb(); 3)Pass NULL to drm_sched_entity_fini_job_cb() if -ENOENT; 4)Replace the type of entity->fini_status with "int"; 5)Remove the check about entity->finished. Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Signed-off-by:
Emily Deng <Emily.Deng@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Andrey Grodzovsky authored
Reserved VRAM is used to avoid overriding pre OS FB. Once our display stack takes over we don't need the reserved VRAM anymore. v2: Remove comment, we know actually why we need to reserve the stolen VRAM. Fix return type for amdgpu_ttm_late_init. v3: Return 0 in amdgpu_bo_late_init, rebase on changes to previous patch v4: rebase v5: For GMC9 reserve always just 9M and keep the stolem memory around until GART table curruption on S3 resume is resolved. Reviewed-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
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Alex Deucher authored
Steal 9 MB for vga emulation and fb if vga is enabled, otherwise, steal enough to cover the current display size as set by the vbios. If no memory is used (e.g., secondary or headless card), skip stolen memory reserve. v2: skip reservation if vram is limited, address Christian's comments v3: squash in fix from Harry Reviewed-and-Tested-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> (v2) Signed-off-by:Alex Deucher <alexdeucher@gmail.com>
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Alex Deucher authored
Use amdgpu_ring_emit_reg_write_reg_wait. On engines that support it, it provides a write and wait in a single packet which avoids a missed ack if a world switch happens between the request and waiting for the ack. Reviewed-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
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Alex Deucher authored
This adds support for writing and reading back using the helper since the engines doesn't have a oneshot packet. Reviewed-by:
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Alex Deucher authored
This adds support for writing and reading back using the helper since the engines doesn't have a oneshot packet. Reviewed-by:
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Alex Deucher authored
This adds support for writing and reading back using the helper since the engines doesn't have a oneshot packet. Reviewed-by:
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Alex Deucher authored
This adds support for writing and reading back in a single oneshot packet. This is needed to send a tlb invalidation and wait for ack in a single operation. v2: squash sdma hang fix into this patch Reviewed-by:
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Alex Deucher authored
This adds support for writing and reading back in a single oneshot packet. This is needed to send a tlb invalidation and wait for ack in a single operation. v2: squash the gfx ring stall fix Reviewed-by:
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Alex Deucher authored
This callback writes a value to a register and then reads back another register and waits for a value in a single operation. Provide a helper function using two operations for engines that don't support this opertion. Reviewed-by:
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Alex Deucher authored
It doesn't actually upload any firmware is just checks the version. The actual upload happens in the gmc modules. Reviewed-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Alex Deucher authored
Fiji uses a different register than other smu7 asics, but we already have this info in the base driver so just use that. Reviewed-by:
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Harry Wentland authored
This seems to cause flickering and lock-ups for a wide range of users. Revert until we've found a proper fix for the flickering and lock-ups. This reverts commit 36cc549d. Cc: Shirish S <shirish.s@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Harry Wentland authored
This reverts commit cd2d6c92. Cc: Shirish S <shirish.s@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by:
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Alex Deucher authored
Userspace needs to query this value to work around a hw bug in certain cases. Acked-by:
Nicolai Hähnle <nicolai.haehnle@amd.com> Signed-off-by:
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Christian König authored
Make sure the transfered BO is never destroy before the transfer BO. Signed-off-by:
Roger He <Hongbo.He@amd.com> Signed-off-by:
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Rex Zhu authored
Only check smc running state before start smu. Reviewed-by:
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Rex Zhu authored
Reviewed-by:
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Kenneth Feng authored
To expose the right dpm levels to the sysfs Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Kenneth Feng authored
To apply on Vega12 for more than 8 gfx dpm levels Signed-off-by:
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Kenneth Feng authored
pp_dpm_sclk/pp_dpm_mclk in sysfs implemented to force gfxclk/uclk dpm level for Vega12 Signed-off-by:
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Rex Zhu authored
1. fix set vce clocks failed on Cz/St which lead 1s delay when boot up. 2. remove the workaround in vce_v3_0.c Reviewed-by:
Shirish S <shirish.s@amd.com> Signed-off-by:
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Rex Zhu authored
fix the issue set uvd clock failed on CZ/ST which lead 1s delay when boot up. Reviewed-by:
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Rex Zhu authored
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Rex Zhu authored
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Shirish S authored
is_blanked() hook is a dummy one for underlay pipe, hence when called, it loops for ~300ms at boot. This patch removes this dummy call and adds missing checks. Signed-off-by:
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Harry Wentland authored
Signed-off-by:
Leo (Sunpeng) Li <sunpeng.li@amd.com> Signed-off-by:
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Harry Wentland authored
We enabled this upstream by default now and no longer need the flag. Signed-off-by:
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Harry Wentland authored
Signed-off-by:
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Christian König authored
The detection if a BO was placed in CPU visible VRAM was incorrect. Fix it and merge it with the correct detection in amdgpu_ttm.c Signed-off-by:
Chunming Zhou <david1.zhou@amd.com> Signed-off-by:
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Christian König authored
Instead of the global (inaccurate) counter. Signed-off-by:
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Evan Quan authored
Signed-off-by:
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Evan Quan authored
pp_soc15.h is vega10 specific. Update powerplay code to use soc15 common macros defined in soc15_common.h. Signed-off-by:
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Evan Quan authored
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Rex Zhu authored
In order to share pp_atomfwctrl_get_vbios_bootup_values on asics with different BIOS_CLKID. Not call function pp_atomfwctrl_get_clk_information_by_clkid in pp_atomfwctrl_get_vbios_bootup_values. Reviewed-by:
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Huang Rui authored
When system uses fw direct loading, then psp context structure won't be initiliazed. And it is also unable to execute mode reset. [ 434.601474] amdgpu 0000:0c:00.0: GPU reset begin! [ 434.694326] amdgpu 0000:0c:00.0: GPU reset [ 434.743152] BUG: unable to handle kernel NULL pointer dereference at 0000000000000058 [ 434.838474] IP: psp_gpu_reset+0xc/0x30 [amdgpu] [ 434.893532] PGD 406ed9067 [ 434.893533] P4D 406ed9067 [ 434.926376] PUD 400b46067 [ 434.959217] PMD 0 [ 435.033379] Oops: 0000 [#1] SMP [ 435.072573] Modules linked in: amdgpu(OE) chash(OE) gpu_sched(OE) ttm(OE) drm_kms_helper(OE) drm(OE) fb_sys_fops syscopyarea sysfillrect sysimgblt rpcsec_gss_krb5 auth_rpcgss nfsv4 nfs lockd grace fscache snd_hda_codec_realtek snd_hda_codec_generic snd_hda_codec_hdmi snd_hda_intel snd_hda_codec snd_hda_core snd_hwdep snd_pcm edac_mce_amd snd_seq_midi snd_seq_midi_event kvm_amd snd_rawmidi kvm irqbypass crct10dif_pclmul crc32_pclmul snd_seq ghash_clmulni_intel snd_seq_device pcbc snd_timer eeepc_wmi aesni_intel snd asus_wmi aes_x86_64 sparse_keymap crypto_simd glue_helper joydev soundcore wmi_bmof cryptd video i2c_piix4 shpchp 8250_dw i2c_designware_platform mac_hid i2c_designware_core sunrpc parport_pc ppdev lp parport autofs4 hid_generic igb usbhid dca ptp mxm_wmi pps_core ahci hid i2c_algo_bit [ 435.931754] libahci wmi Signed-off-by:
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Nico Sneck authored
With this the dGPU turns on correctly. Signed-off-by:
Nico Sneck <nicosneck@hotmail.com> Signed-off-by:
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Leo (Sunpeng) Li authored
Input transfer function creation is now done when the plane is created. This is done within the following change: Author: Anthony Koo <Anthony.Koo@amd.com> drm/amd/display: Have DC manage its own allocation of gamma Therefore, we no longer need to create it when filling in the plane attributes. Signed-off-by: -
Leo (Sunpeng) Li authored
Before programming the input gamma, check that we're not using the identity correction. Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Anthony Koo authored
Creating plane will also allocate gamma and input TF Creating stream will also allocate outputTF Fix issue with gamma not applied OS may call SetGamma before surface committed, so need to store in target and apply later. Signed-off-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
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