1. 09 Feb, 2017 2 commits
  2. 08 Feb, 2017 14 commits
  3. 07 Feb, 2017 6 commits
    • Paolo Bonzini's avatar
      Merge tag 'kvm-s390-next-4.11-2' of... · 8f00067a
      Paolo Bonzini authored
      Merge tag 'kvm-s390-next-4.11-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kvms390/linux into HEAD
      
      KVM: s390: Fixes and features for 4.11 (via kvm/next)
      
      - enable some simd extensions for guests
      - enable nx for guests
      - debug log for cpu model
      - PER fixes
      - remove bitwise annotation from ar_t
      - detect guests in operation exception program check loops
      - fix potential null-pointer dereference for ucontrol guests
      
      - also contains merge for fix that went into 4.10 to avoid conflicts
      8f00067a
    • Paolo Bonzini's avatar
      Merge tag 'kvm_mips_4.11_1' of... · d9c0e59f
      Paolo Bonzini authored
      Merge tag 'kvm_mips_4.11_1' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/kvm-mips into HEAD
      
      KVM: MIPS: GVA/GPA page tables, dirty logging, SYNC_MMU etc
      
      Numerous MIPS KVM fixes, improvements, and features for 4.11, many of
      which continue to pave the way for VZ support, the most interesting of
      which are:
      
       - Add GVA->HPA page tables for T&E, to cache GVA mappings.
       - Generate fast-path TLB refill exception handler which loads host TLB
         entries from GVA page table, avoiding repeated guest memory
         translation and guest TLB lookups.
       - Use uaccess macros when T&E needs to access guest memory, which with
         GVA page tables and the Linux TLB refill handler improves robustness
         against TLB faults and fixes EVA hosts.
       - Use BadInstr/BadInstrP registers when available to obtain instruction
         encodings after a synchronous trap.
       - Add GPA->HPA page tables to replace the inflexible linear array,
         allowing for multiple sparsely arranged memory regions.
       - Properly implement dirty page logging.
       - Add KVM_CAP_SYNC_MMU support so that changes in GPA mappings become
         effective in guests even if they are already running, allowing for
         copy-on-write, KSM, idle page tracking, swapping, and guest memory
         ballooning.
       - Add KVM_CAP_READONLY_MEM support, so writes to specified memory
         regions are treated as MMIO.
       - Implement proper CP0_EBase support in T&E.
       - Expose a few more missing CP0 registers to userland.
       - Add KVM_CAP_NR_VCPUS and KVM_CAP_MAX_VCPUS support, and allow up to 8
         VCPUs to be created in a VM.
       - Various cleanups and dropping of dead and duplicated code.
      d9c0e59f
    • Paolo Bonzini's avatar
      Merge branch 'kvm-ppc-next' of... · d5b798c1
      Paolo Bonzini authored
      Merge branch 'kvm-ppc-next' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc into HEAD
      
      The big feature this time is support for POWER9 using the radix-tree
      MMU for host and guest.  This required some changes to arch/powerpc
      code, so I talked with Michael Ellerman and he created a topic branch
      with this patchset, which I merged into kvm-ppc-next and which Michael
      will pull into his tree.  Michael also put in some patches from Nick
      Piggin which fix bugs in the interrupt vector code in relocatable
      kernels when coming from a KVM guest.
      
      Other notable changes include:
      
      * Add the ability to change the size of the hashed page table,
        from David Gibson.
      
      * XICS (interrupt controller) emulation fixes and improvements,
        from Li Zhong.
      
      * Bug fixes from myself and Thomas Huth.
      
      These patches define some new KVM capabilities and ioctls, but there
      should be no conflicts with anything else currently upstream, as far
      as I am aware.
      d5b798c1
    • Marcelo Tosatti's avatar
      KVM: x86: add KVM_HC_CLOCK_PAIRING hypercall · 55dd00a7
      Marcelo Tosatti authored
      Add a hypercall to retrieve the host realtime clock and the TSC value
      used to calculate that clock read.
      
      Used to implement clock synchronization between host and guest.
      Signed-off-by: default avatarMarcelo Tosatti <mtosatti@redhat.com>
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      55dd00a7
    • David Hildenbrand's avatar
      KVM: nVMX: vmx_complete_nested_posted_interrupt() can't fail · 6342c50a
      David Hildenbrand authored
      vmx_complete_nested_posted_interrupt() can't fail, let's turn it into
      a void function.
      Signed-off-by: default avatarDavid Hildenbrand <david@redhat.com>
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      6342c50a
    • David Hildenbrand's avatar
      KVM: nVMX: kmap() can't fail · 42cf014d
      David Hildenbrand authored
      kmap() can't fail, therefore it will always return a valid pointer. Let's
      just get rid of the unnecessary checks.
      Signed-off-by: default avatarDavid Hildenbrand <david@redhat.com>
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      42cf014d
  4. 06 Feb, 2017 2 commits
  5. 03 Feb, 2017 16 commits
    • James Hogan's avatar
      KVM: MIPS: Allow multiple VCPUs to be created · 12ed1fae
      James Hogan authored
      Increase the maximum number of MIPS KVM VCPUs to 8, and implement the
      KVM_CAP_NR_VCPUS and KVM_CAP_MAX_CPUS capabilities which expose the
      recommended and maximum number of VCPUs to userland. The previous
      maximum of 1 didn't allow for any form of SMP guests.
      
      We calculate the values similarly to ARM, recommending as many VCPUs as
      there are CPUs online in the system. This will allow userland to know
      how many VCPUs it is possible to create.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: "Radim Krčmář" <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      12ed1fae
    • James Hogan's avatar
      KVM: MIPS/T&E: Expose read-only CP0_IntCtl register · ad58d4d4
      James Hogan authored
      Expose the CP0_IntCtl register through the KVM register access API,
      which is a required register since MIPS32r2. It is currently read-only
      since the VS field isn't implemented due to lack of Config3.VInt or
      Config3.VEIC.
      
      It is implemented in trap_emul.c so that a VZ implementation can allow
      writes.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: "Radim Krčmář" <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      ad58d4d4
    • James Hogan's avatar
      KVM: MIPS/T&E: Expose CP0_EntryLo0/1 registers · 013044cc
      James Hogan authored
      Expose the CP0_EntryLo0 and CP0_EntryLo1 registers through the KVM
      register access API. This is fairly straightforward for trap & emulate
      since we don't support the RI and XI bits. For the sake of future
      proofing (particularly for VZ) it is explicitly specified that the API
      always exposes the 64-bit version of these registers (i.e. with the RI
      and XI bits in bit positions 63 and 62 respectively), and they are
      implemented in trap_emul.c rather than mips.c to allow them to be
      implemented differently for VZ.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: "Radim Krčmář" <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      013044cc
    • James Hogan's avatar
      KVM: MIPS/T&E: Default to reset vector · be67a0be
      James Hogan authored
      Set the default VCPU state closer to the architectural reset state, with
      PC pointing at the reset vector (uncached PA 0x1fc00000, which for KVM
      T&E is VA 0x5fc00000), and with CP0_Status.BEV and CP0_Status.ERL to 1.
      
      Although QEMU at least will overwrite this state, it makes sense to do
      this now that CP0_EBase is properly implemented to check BEV, and now
      that we support a sparse GPA layout potentially with a boot ROM at GPA
      0x1fc00000.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: "Radim Krčmář" <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      be67a0be
    • James Hogan's avatar
      KVM: MIPS/T&E: Implement CP0_EBase register · 7801bbe1
      James Hogan authored
      The CP0_EBase register is a standard feature of MIPS32r2, so we should
      always have been implementing it properly. However the register value
      was ignored and wasn't exposed to userland.
      
      Fix the emulation of exceptions and interrupts to use the value stored
      in guest CP0_EBase, and fix the masks so that the top 3 bits (rather
      than the standard 2) are fixed, so that it is always in the guest KSeg0
      segment.
      
      Also add CP0_EBASE to the KVM one_reg interface so it can be accessed by
      userland, also allowing the CPU number field to be written (which isn't
      permitted by the guest).
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: "Radim Krčmář" <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      7801bbe1
    • James Hogan's avatar
      KVM: MIPS/T&E: Move CP0 register access into T&E · 654229a0
      James Hogan authored
      Access to various CP0 registers via the KVM register access API needs to
      be implementation specific to allow restrictions to be made on changes,
      for example when VZ guest registers aren't present, so move them all
      into trap_emul.c in preparation for VZ.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: "Radim Krčmář" <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      654229a0
    • James Hogan's avatar
      KVM: MIPS: Claim KVM_CAP_READONLY_MEM support · 230c5724
      James Hogan authored
      Now that load/store faults due to read only memory regions are treated
      as MMIO accesses it is safe to claim support for read only memory
      regions (KVM_CAP_READONLY_MEM).
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: "Radim Krčmář" <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      230c5724
    • James Hogan's avatar
      KVM: MIPS/MMU: Implement KVM_CAP_SYNC_MMU · 411740f5
      James Hogan authored
      Implement the SYNC_MMU capability for KVM MIPS, allowing changes in the
      underlying user host virtual address (HVA) mappings to be promptly
      reflected in the corresponding guest physical address (GPA) mappings.
      
      This allows for several features to work with guest RAM which require
      mappings to be altered or protected, such as copy-on-write, KSM (Kernel
      Samepage Merging), idle page tracking, memory swapping, and guest memory
      ballooning.
      
      There are two main aspects of this change, described below.
      
      The KVM MMU notifier architecture callbacks are implemented so we can be
      notified of changes in the HVA mappings. These arrange for the guest
      physical address (GPA) page tables to be modified and possibly for
      derived mappings (GVA page tables and TLBs) to be flushed.
      
       - kvm_unmap_hva[_range]() - These deal with HVA mappings being removed,
         for example before a copy-on-write takes place, which requires the
         corresponding GPA page table mappings to be removed too.
      
       - kvm_set_spte_hva() - These update a GPA page table entry to match the
         new HVA entry, but must be careful to respect KVM specific
         configuration such as not dirtying a clean guest page which is dirty
         to the host, and write protecting writable pages in read only
         memslots (which will soon be supported).
      
       - kvm[_test]_age_hva() - These update GPA page table entries to be old
         (invalid) so that access can be tracked, making them young again.
      
      The GPA page fault handling (kvm_mips_map_page) is updated to use
      gfn_to_pfn_prot() (which may provide read-only pages), to handle
      asynchronous page table invalidation from MMU notifier callbacks, and to
      handle more cases in the fast path.
      
       - mmu_notifier_seq is used to detect asynchronous page table
         invalidations while we're holding a pfn from gfn_to_pfn_prot()
         outside of kvm->mmu_lock, retrying if invalidations have taken place,
         e.g. a COW or a KSM page merge.
      
       - The fast path (_kvm_mips_map_page_fast) now handles marking old pages
         as young / accessed, and disallowing dirtying of clean pages that
         aren't actually writable (e.g. shared pages that should COW, and
         read-only memory regions when they are enabled in a future patch).
      
       - Due to the use of MMU notifications we no longer need to keep the
         page references after we've updated the GPA page tables.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: "Radim Krčmář" <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      411740f5
    • James Hogan's avatar
      KVM: MIPS/MMU: Pass GPA PTE bits to mapped GVA PTEs · f9b11e51
      James Hogan authored
      Propagate the GPA PTE protection bits on to the GVA PTEs on a mapped
      fault (except _PAGE_WRITE, and filtered by the guest TLB entry), rather
      than always overriding the protection. This allows dirty page tracking
      to work in mapped guest segments as a clear dirty bit in the GPA PTE
      will propagate to the GVA PTEs even when the guest TLB has the dirty bit
      set.
      
      Since the filtering of protection bits is now abstracted, if the buddy
      GVA PTE is also valid, we obtain the corresponding GPA PTE using a
      simple non-allocating walk and load that into the GVA PTE similarly
      (which may itself be invalid).
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: "Radim Krčmář" <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      f9b11e51
    • James Hogan's avatar
      KVM: MIPS/MMU: Pass GPA PTE bits to KSeg0 GVA PTEs · b584f460
      James Hogan authored
      Propagate the GPA PTE protection bits on to the GVA PTEs on a KSeg0
      fault (except _PAGE_WRITE), rather than always overriding the
      protection. This allows dirty page tracking to work in KSeg0 as a clear
      dirty bit in the GPA PTE will propagate to the GVA PTEs.
      
      This makes it simpler to use a single kvm_mips_map_page() to obtain both
      the main GPA PTE and its buddy (which may be invalid), which also allows
      memory regions to be fully accessible when they don't start and end on a
      2*PAGE_SIZE boundary.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: "Radim Krčmář" <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      b584f460
    • James Hogan's avatar
      KVM: MIPS/MMU: Handle dirty logging on GPA faults · b5f1dd1b
      James Hogan authored
      Update kvm_mips_map_page() to handle logging of dirty guest physical
      pages. Upcoming patches will propagate the dirty bit to the GVA page
      tables.
      
      A fast path is added for handling protection bits that can be resolved
      without calling into KVM, currently just dirtying of clean pages being
      written to.
      
      The slow path marks the GPA page table entry writable only on writes,
      and at the same time marks the page dirty in the dirty page logging
      bitmask.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: "Radim Krčmář" <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      b5f1dd1b
    • James Hogan's avatar
      KVM: MIPS: Clean & flush on dirty page logging enable · a1ac9e17
      James Hogan authored
      When an existing memory region has dirty page logging enabled, make the
      entire slot clean (read only) so that writes will immediately start
      logging dirty pages (once the dirty bit is transferred from GPA to GVA
      page tables in an upcoming patch).
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: "Radim Krčmář" <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      a1ac9e17
    • James Hogan's avatar
      KVM: MIPS/MMU: Use generic dirty log & protect helper · e88643ba
      James Hogan authored
      MIPS hasn't up to this point properly supported dirty page logging, as
      pages in slots with dirty logging enabled aren't made clean, and tlbmod
      exceptions from writes to clean pages have been assumed to be due to
      guest TLB protection and unconditionally passed to the guest.
      
      Use the generic dirty logging helper kvm_get_dirty_log_protect() to
      properly implement kvm_vm_ioctl_get_dirty_log(), similar to how ARM
      does. This uses xchg to clear the dirty bits when reading them, rather
      than wiping them out afterwards with a memset, which would potentially
      wipe recently set bits that weren't caught by kvm_get_dirty_log(). It
      also makes the pages clean again using the
      kvm_arch_mmu_enable_log_dirty_pt_masked() architecture callback so that
      further writes after the shadow memslot is flushed will trigger tlbmod
      exceptions and dirty handling.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: "Radim Krčmář" <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      e88643ba
    • James Hogan's avatar
      KVM: MIPS/MMU: Add GPA PT mkclean helper · f0c0c330
      James Hogan authored
      Add a helper function to make a range of guest physical address (GPA)
      mappings in the GPA page table clean so that writes can be caught. This
      will be used in a few places to manage dirty page logging.
      
      Note that until the dirty bit is transferred from GPA page table entries
      to GVA page table entries in an upcoming patch this won't trigger a TLB
      modified exception on write.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: "Radim Krčmář" <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      f0c0c330
    • James Hogan's avatar
      KVM: MIPS/T&E: Handle read only GPA in TLB mod · 64ebc9e2
      James Hogan authored
      Rewrite TLB modified exception handling to handle read only GPA memory
      regions, instead of unconditionally passing the exception to the guest.
      
      If the guest TLB is not the cause of the exception we call into the
      normal TLB fault handling depending on the memory segment, which will
      soon attempt to remap the physical page to be writable (handling dirty
      page tracking or copy on write in the process).
      
      Failing that we fall back to treating it as MMIO, due to a read only
      memory region. Once the capability is enabled, this will allow read only
      memory regions (such as the Malta boot flash as emulated by QEMU) to
      have writes treated as MMIO, while still allowing reads to run
      untrapped.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: "Radim Krčmář" <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      64ebc9e2
    • James Hogan's avatar
      KVM: MIPS/T&E: Treat unhandled guest KSeg0 as MMIO · b8f79ddb
      James Hogan authored
      Treat unhandled accesses to guest KSeg0 as MMIO, rather than only host
      KSeg0 addresses. This will allow read only memory regions (such as the
      Malta boot flash as emulated by QEMU) to have writes (before reads)
      treated as MMIO, and unallocated physical addresses to have all accesses
      treated as MMIO.
      
      The MMIO emulation uses the gva_to_gpa callback, so this is also updated
      for trap & emulate to handle guest KSeg0 addresses.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: "Radim Krčmář" <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      b8f79ddb