- 04 May, 2023 9 commits
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Leo Chen authored
[Why & How] Previous Z8 watermark values were causing flickering and OTC underflow. Updating Z8 watermark values based on the measurement. Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Acked-by:
Alan Liu <HaoPing.Liu@amd.com> Signed-off-by:
Leo Chen <sancchen@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Horace Chen authored
[Why] This WPTR_POLL_ENABLE is a hardware contigious polling which will cause FCLK and UCLK to keep on a high level. Mostly its case can be covered by F32_WPTR_POLL_ENABLE which polls by firmware. So to save power, SR-IOV also needs to disable this bit Signed-off-by:
Horace Chen <horace.chen@amd.com> Acked-by:
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Chia-I Wu authored
mgr->ctx_handles should be protected by mgr->lock. v2: improve commit message v3: add a Fixes tag Signed-off-by:
Chia-I Wu <olvaffe@gmail.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Fixes: 52c6a62c ("drm/amdgpu: add interface for editing a foreign process's priority v3") Signed-off-by:
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Hamza Mahfooz authored
As made mention of in commit 08c677cb ("drm/amdgpu: fix amdgpu_irq_put call trace in gmc_v10_0_hw_fini") and commit 13af5561 ("drm/amdgpu: fix amdgpu_irq_put call trace in gmc_v11_0_hw_fini"). It is meaningless to call amdgpu_irq_put() for gmc.ecc_irq. So, remove it from gmc_v9_0_hw_fini(). Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2522 Fixes: 3029c855d79f ("drm/amdgpu: Fix desktop freezed after gpu-reset") Reviewed-by:
Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Horatio Zhang authored
The gmc.ecc_irq is enabled by firmware per IFWI setting, and the host driver is not privileged to enable/disable the interrupt. So, it is meaningless to use the amdgpu_irq_put function in gmc_v10_0_hw_fini, which also leads to the call trace. [ 82.340264] Call Trace: [ 82.340265] <TASK> [ 82.340269] gmc_v10_0_hw_fini+0x83/0xa0 [amdgpu] [ 82.340447] gmc_v10_0_suspend+0xe/0x20 [amdgpu] [ 82.340623] amdgpu_device_ip_suspend_phase2+0x127/0x1c0 [amdgpu] [ 82.340789] amdgpu_device_ip_suspend+0x3d/0x80 [amdgpu] [ 82.340955] amdgpu_device_pre_asic_reset+0xdd/0x2b0 [amdgpu] [ 82.341122] amdgpu_device_gpu_recover.cold+0x4dd/0xbb2 [amdgpu] [ 82.341359] amdgpu_debugfs_reset_work+0x4c/0x70 [amdgpu] [ 82.341529] process_one_work+0x21d/0x3f0 [ 82.341535] worker_thread+0x1fa/0x3c0 [ 82.341538] ? process_one_work+0x3f0/0x3f0 [ 82.341540] kthread+0xff/0x130 [ 82.341544] ? kthread_complete_and_exit+0x20/0x20 [ 82.341547] ret_from_fork+0x22/0x30 Signed-off-by:
Horatio Zhang <Hongkun.Zhang@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Horatio Zhang authored
The gmc.ecc_irq is enabled by firmware per IFWI setting, and the host driver is not privileged to enable/disable the interrupt. So, it is meaningless to use the amdgpu_irq_put function in gmc_v11_0_hw_fini, which also leads to the call trace. [ 102.980303] Call Trace: [ 102.980303] <TASK> [ 102.980304] gmc_v11_0_hw_fini+0x54/0x90 [amdgpu] [ 102.980357] gmc_v11_0_suspend+0xe/0x20 [amdgpu] [ 102.980409] amdgpu_device_ip_suspend_phase2+0x240/0x460 [amdgpu] [ 102.980459] amdgpu_device_ip_suspend+0x3d/0x80 [amdgpu] [ 102.980520] amdgpu_device_pre_asic_reset+0xd9/0x490 [amdgpu] [ 102.980573] amdgpu_device_gpu_recover.cold+0x548/0xce6 [amdgpu] [ 102.980687] amdgpu_debugfs_reset_work+0x4c/0x70 [amdgpu] [ 102.980740] process_one_work+0x21f/0x3f0 [ 102.980741] worker_thread+0x200/0x3e0 [ 102.980742] ? process_one_work+0x3f0/0x3f0 [ 102.980743] kthread+0xfd/0x130 [ 102.980743] ? kthread_complete_and_exit+0x20/0x20 [ 102.980744] ret_from_fork+0x22/0x30 Signed-off-by:
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Shane Xiao authored
[Why] The selfring doorbell aperture will change when resize FB BAR successfully during gmc sw init, we should reorder the sequence of enabling doorbell selfring aperture. [How] Move enable_doorbell_selfring_aperture from *_common_hw_init to *_common_late_init. This fixes the potential issue that GPU ring its own doorbell when this device is in translated mode when iommu is on. v2: Remove *_enable_doorbell_aperture functions (Christian) v3: Add comments to note that why we need enable doorbell selfring late (Christian) Signed-off-by:Shane Xiao <shane.xiao@amd.com> Signed-off-by:
Aaron Liu <aaron.liu@amd.com> Tested-by:
Xiaomeng Hou <Xiaomeng.Hou@amd.com> Reviewed-by:
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lyndonli authored
Below call trace and errors are observed when reloading amdgpu driver with the module parameter reset_method=3. It should do a default reset when loading or reloading the driver, regardless of the module parameter reset_method. v2: add comments inside and modify commit messages. [ +2.180243] [drm] psp gfx command ID_LOAD_TOC(0x20) failed and response status is (0x0) [ +0.000011] [drm:psp_hw_start [amdgpu]] *ERROR* Failed to load toc [ +0.000890] [drm:psp_hw_start [amdgpu]] *ERROR* PSP tmr init failed! [ +0.020683] [drm:amdgpu_fill_buffer [amdgpu]] *ERROR* Trying to clear memory with ring turned off. [ +0.000003] RIP: 0010:amdgpu_bo_release_notify+0x1ef/0x210 [amdgpu] [ +0.000004] Call Trace: [ +0.000003] <TASK> [ +0.000008] ttm_bo_release+0x2c4/0x330 [amdttm] [ +0.000026] amdttm_bo_put+0x3c/0x70 [amdttm] [ +0.000020] amdgpu_bo_free_kernel+0xe6/0x140 [amdgpu] [ +0.000728] psp_v11_0_ring_destroy+0x34/0x60 [amdgpu] [ +0.000826] psp_hw_init+0xe7/0x2f0 [amdgpu] [ +0.000813] amdgpu_device_fw_loading+0x1ad/0x2d0 [amdgpu] [ +0.000731] amdgpu_device_init.cold+0x108e/0x2002 [amdgpu] [ +0.001071] ? do_pci_enable_device+0xe1/0x110 [ +0.000011] amdgpu_driver_load_kms+0x1a/0x160 [amdgpu] [ +0.000729] amdgpu_pci_probe+0x179/0x3a0 [amdgpu] Signed-off-by:
lyndonli <Lyndon.Li@amd.com> Signed-off-by:
Yunxiang Li <Yunxiang.Li@amd.com> Reviewed-by:
Feifei Xu <Feifei.Xu@amd.com> Reviewed-by:
Kenneth Feng <kenneth.feng@amd.com> Signed-off-by:
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lyndonli authored
Before this change, sienna_cichlid_get_reset_handler will always return NULL, although the module parameter reset_method is 3 when loading amdgpu driver. Signed-off-by:
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- 27 Apr, 2023 22 commits
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Leo Chen authored
[Why & How] Per HW team request, we're lowering the minimum Z8 residency time to 2000us. This enables Z8 support for additional modes we were previously blocking like 2k>60hz Cc: stable@vger.kernel.org Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Hamza Mahfooz authored
Currently, on a handful of ASICs. We allow the framebuffer for a given plane to exist in either VRAM or GTT. However, if the plane's new framebuffer is in a different memory domain than it's previous framebuffer, flipping between them can cause the screen to flicker. So, to fix this, don't perform an immediate flip in the aforementioned case. Cc: stable@vger.kernel.org Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2354Reviewed-by:
Roman Li <Roman.Li@amd.com> Fixes: 81d0bcf9 ("drm/amdgpu: make display pinning more flexible (v2)") Signed-off-by:
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Igor Kravchenko authored
Add min_width, min_height fields to dc_plane_cap structure. Set values to 16x16 for discrete ASICs, and 64x64 for others. Reviewed-by:
Igor Kravchenko <Igor.Kravchenko@amd.com> Tested-by:
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Jasdeep Dhillon authored
[Why] DCN32 resource contains code that uses FPU. [How] Moved code into DCN32 FPU Reviewed-by:
Jasdeep Dhillon <jasdeep.dhillon@amd.com> Tested-by:
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Aurabindo Pillai authored
[Why&how] Update bounding box values as per hardware spec Fixes: 197485c6 ("drm/amd/display: Create dcn321_fpu file") Acked-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by:
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Aurabindo Pillai authored
[Why & How] There's no need to clear GPINT register for DMUB when releasing it from reset. Fix that. Fixes: ac2e555e ("drm/amd/display: Add DMCUB source files and changes for DCN32/321") Reviewed-by:
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Cruise Hung authored
[Why & How] We missed resetting OUTBOX0 mailbox r/w pointer on DMUB reset. Fix it. Fixes: 6ecf9773 ("drm/amd/display: Fix DMUB outbox trace in S4 (#4465)") Signed-off-by:
Cruise Hung <Cruise.Hung@amd.com> Acked-by:
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Aurabindo Pillai authored
[Why&How] Fix CLK MGR early initialization and add logging. Fixes: 265280b9 ("drm/amd/display: add CLKMGR changes for DCN32/321") Reviewed-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by:
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Tianci Yin authored
[why] Since the variable fpu_recursion_depth is per-CPU type, it has one copy on each CPU, thread migration causes data consistency issue, then the call trace shows up. And preemption disabling can't prevent migration. [how] Disable migration to ensure consistency of fpu_recursion_depth. Reviewed-by:
Tianci Yin <tianci.yin@amd.com> Tested-by:
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Aurabindo Pillai authored
[Why&How] Remove incorrect early return in a device specific fifo reset workaround Reviewed-by:
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Hersen Wu authored
[Why&How] We were not returning -EINVAL on DSC atomic check fail. Add it. Fixes: 71be4b16 ("drm/amd/display: dsc validate fail not pass to atomic check") Reviewed-by:
Hersen Wu <hersenxs.wu@amd.com> Tested-by:
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Jingwen Zhu authored
[Why] The eDP retrain will cause the DPCD 300 to be reset to default. And cause the brightness can't be set correctly. [How] delete the call to edp panel power control in both enable_link_output/disable_link_output entirely and only call edp panel control in enable_link_dp and disable_link_dp once. Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
Jingwen Zhu <Jingwen.Zhu@amd.com> Tested-by:
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Michael Mityushkin authored
[Why] When link training during engine recovery, ASSR might fail causing panel mode to be reset to default. This should not happen for eDP as it will prevent the panel from turning back on. [How] Added dp_panel_mode to struct dc_link to remember previously applied panel mode. Do not reset panel mode to default while performing link training if previously used panel mode = eDP. Reviewed-by:
Michael Mityushkin <michael.mityushkin@amd.com> Tested-by:
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Hersen Wu authored
[Why] hdcp are enabled for asics from raven. for old asics which hdcp are not enabled, hdcp_workqueue are null. some access to hdcp work queue are not guarded with pointer check. [How] add hdcp_workqueue pointer check before access workqueue. Fixes: 82986fd6 ("drm/amd/display: save restore hdcp state when display is unplugged from mst hub") Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2444Reported-by:
Niklāvs Koļesņikovs <89q1r14hd@relay.firefox.com> Reviewed-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by:
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Alvin Lee authored
[Description] - Having excessively large margin causes failure in the static schedulability check in some cases for SubVP + DRR - 100us of DRR margin is sufficient based on a weeks worth of stress testing on different display configs Reviewed-by:
Michael Strauss <Michael.Strauss@amd.com> Acked-by:
Alvin Lee <Alvin.Lee2@amd.com> Tested-by:
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Hersen Wu authored
[Why] when amdgpu_dm_update_connector_after_detect is called two times successively with valid sink, memory allocated of aconnector->timing_requested for the first call is not free. this causes memeleak. [How] allocate memory only when aconnector->timing_requested is null. Reviewed-by:
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Aurabindo Pillai authored
[Why&How] When skipping full modeset since the only state change was a front porch change, the DC commit sequence requires extra checks to handle non existant plane states being asked to be removed from context. Reviewed-by:
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Alex Hung authored
[Why] When IGT's kms_hdmi_inject forces EDID for HDMI audio, dc rejects the request because virtual signal is not in dc_is_audio_capable_signal function. [How] Includes SIGNAL_TYPE_VIRTUAL as audio capable. Reviewed-by:
Chao-kai Wang <Stylon.Wang@amd.com> Acked-by:
Alex Hung <alex.hung@amd.com> Signed-off-by:
Wenchieh Chien <wenchieh.chien@amd.com> Tested-by:
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Josip Pavic authored
[Why & How] Add code path to copy dmub caps to dc, which is missing on dcn31 Acked-by:
Josip Pavic <Josip.Pavic@amd.com> Tested-by:
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Rodrigo Siqueira authored
When the commit fff7eb56 ("drm/amd/display: Don't set dram clock change requirement for SubVP") was merged, we missed some parts associated with the MCLK switch. This commit adds all the missing parts. Fixes: fff7eb56 ("drm/amd/display: Don't set dram clock change requirement for SubVP") Reviewed-by:
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Wesley Chalmers authored
[WHY] It is possible to commit state multiple times in rapid succession with FAMS enabled; if each of these commits were to set optimized_required, then the user may see latency. [HOW] fw_based_mclk_switching is currently not used in dc->clk_mgr; use it to track whether the current state has FAMS enabled; if it has, then do not disable FAMS in prepare_bandwidth, and do not set optimized_required. Reviewed-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Tested-by:
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Wesley Chalmers authored
[WHY] Writing to DRR registers such as OTG_V_TOTAL_MIN on the same frame as a pipe commit can cause underflow. [HOW] Move DMUB p-state delegate into optimze_bandwidth; enabling FAMS sets optimized_required. This change expects that Freesync requests are blocked when optimized_required is true. Reviewed-by:
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- 18 Apr, 2023 9 commits
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Tom Rix authored
smatch reports drivers/gpu/drm/amd/amdgpu/../display/dc/dcn314/dcn314_dccg.c:277:6: warning: symbol 'dccg314_init' was not declared. Should it be static? This variable is only used in one file so should be static. Signed-off-by:
Tom Rix <trix@redhat.com> Signed-off-by:
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Rodrigo Siqueira authored
Reviewed-by:
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Rodrigo Siqueira authored
Reviewed-by:
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Rodrigo Siqueira authored
Reviewed-by:
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Rodrigo Siqueira authored
Reviewed-by:
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Rodrigo Siqueira authored
This commit replaces spaces with tabs in multiple functions and adjusts the indentation in some other parts of the code to improve readability. Reviewed-by:
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Rodrigo Siqueira authored
When using FPO, there is some misconfiguration that happens for the lack of configuration of the MCLK switch in some circumstances. This commit adds the required field update when using the MCLK switch. Reviewed-by:
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Rodrigo Siqueira authored
All clock values came from firmware, but bounding box values can be helpful in some debug situations. This commit updates some of the values associated with clock speed and memory channels. Reviewed-by:
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Chong Li authored
[WHY] Function "amdgpu_irq_update()" called by "amdgpu_device_ip_late_init()" is an atomic context. We shouldn't access registers through KIQ since "msleep()" may be called in "amdgpu_kiq_rreg()". [HOW] Move function "amdgpu_virt_release_full_gpu()" after function "amdgpu_device_ip_late_init()", to ensure that registers be accessed through RLCG instead of KIQ. Call Trace: <TASK> show_stack+0x52/0x69 dump_stack_lvl+0x49/0x6d dump_stack+0x10/0x18 __schedule_bug.cold+0x4f/0x6b __schedule+0x473/0x5d0 ? __wake_up_klogd.part.0+0x40/0x70 ? vprintk_emit+0xbe/0x1f0 schedule+0x68/0x110 schedule_timeout+0x87/0x160 ? timer_migration_handler+0xa0/0xa0 msleep+0x2d/0x50 amdgpu_kiq_rreg+0x18d/0x1f0 [amdgpu] amdgpu_device_rreg.part.0+0x59/0xd0 [amdgpu] amdgpu_device_rreg+0x3a/0x50 [amdgpu] amdgpu_sriov_rreg+0x3c/0xb0 [amdgpu] gfx_v10_0_set_gfx_eop_interrupt_state.constprop.0+0x16c/0x190 [amdgpu] gfx_v10_0_set_eop_interrupt_state+0xa5/0xb0 [amdgpu] amdgpu_irq_update+0x53/0x80 [amdgpu] amdgpu_irq_get+0x7c/0xb0 [amdgpu] amdgpu_fence_driver_hw_init+0x58/0x90 [amdgpu] amdgpu_device_init.cold+0x16b7/0x2022 [amdgpu] Signed-off-by:
Chong Li <chongli2@amd.com> Reviewed-by: JingWen.Chen2@amd.com Signed-off-by:
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