* '4.15-rc1-clkctrl-driver' of https://github.com/t-kristo/linux-pm: (28 commits)
  clk: ti: omap4: clkctrl data fixes for opt-clocks
  clk: ti: dm816: add clkctrl clock data
  dt-bindings: clk: add dm816 clkctrl definitions
  clk: ti: dm814: add clkctrl clock data
  dt-bindings: clk: add dm814 clkctrl definitions
  clk: ti: am43xx: add clkctrl clock data
  dt-bindings: clk: add am43xx clkctrl definitions
  clk: ti: am33xx: add clkctrl clock data
  dt-bindings: clk: add am33xx clkctrl definitions
  clk: ti: dra7: add clkctrl clock data
  dt-bindings: clk: add dra7 clkctrl definitions
  clk: ti: omap5: add clkctrl clock data
  dt-bindings: clk: add omap5 clkctrl definitions
  clk: ti: omap3: cleanup unnecessary clock aliases
  clk: ti: am43xx: cleanup unnecessary clock aliases
  clk: ti: am33xx: cleanup unnecessary clock aliases
  clk: ti: dm816x: cleanup unnecessary clock aliases
  clk: ti: dm814x: cleanup unnecessary clock aliases
  clk: ti: omap5: cleanup unnecessary clock aliases
  clk: ti: dra7: drop unnecessary clock aliases
  ...

* clk-stm32-copyright:
  clk: stm32-h7: fix copyright

Uniformize STMicroelectronics copyrights header
Add SPDX identifier
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
Acked-by: Alexandre TORGUE <alexandre.torgue@st.com>
CC: Gabriel Fernandez <gabriel.fernandez@st.com>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Acked-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

* clk-hi3660-stub:
  clk: hisilicon: Add support for Hi3660 stub clocks
  dt-bindings: clk: Hi3660: Document stub clock

Hi3660 has four stub clocks, which are big and LITTLE cluster clocks,
GPU clock and DDR clock.  These clocks ask MCU for frequency scaling
by sending message through mailbox.

This commit adds support for stub clocks, it requests the dedicated
mailbox channel at initialization; then later uses this channel to send
message to MCU to execute frequency scaling. The four stub clocks share
the same mailbox channel, but every stub clock has its own command id so
MCU can distinguish the requirement coming for which clock.

A shared memory is used to present effective frequency value, so the
clock driver uses I/O mapping for the memory and reads back rate value.
Reviewed-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Kai Zhao <zhaokai1@hisilicon.com>
Signed-off-by: Tao Wang <kevin.wangtao@hisilicon.com>
Signed-off-by: Ruyi Wang <wangruyi@huawei.com>
Signed-off-by: Kaihua Zhong <zhongkaihua@huawei.com>
[sboyd: Fix possible out of bounds access in hi3660_stub_clk_hw_get(),
        use devm_of_clk_add_hw_provider(), devm_ioremap() returns
	NULL not error pointers]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

Document the DT binding for stub clock which is used for CPU,
GPU and DDR frequency scaling.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

* clk-pr-err:
  clk: h8300: pr_err() strings should end with newlines
  clk: h8s2678: pr_err() strings should end with newlines
  SPEAr: clk: pr_err() strings should end with newlines
  clk: SPEAr: pr_err() strings should end with newlines
  clk: lpc32xx: pr_err() strings should end with newlines
  clk: stm32f4: pr_err() strings should end with newlines

pr_err() messages should end with a new-line to avoid other messages
being concatenated.
Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

pr_err() messages should end with a new-line to avoid other messages
being concatenated.
Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

pr_err() messages should end with a new-line to avoid other messages
being concatenated.
Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

pr_err() messages should end with a new-line to avoid other messages
being concatenated.
Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

pr_err() messages should end with a new-line to avoid other messages
being concatenated.
Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com>
Acked-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

pr_err() messages should end with a new-line to avoid other messages
being concatenated.
Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

* clk-qcom-spmi-div:
  clk: qcom: Add spmi_pmic clock divider support
  dt-bindings: Add qcom spmi_pmic clock divider bindings

* clk-qcom-audio-fixes:
  clk: qcom: msm8916: add 12.288 MHz support to codec dig clk
  clk: qcom: msm8916: fix mnd_width for codec_digcodec
  clk: qcom: msm8916: Fix i2s clk rates required for mclk

This patch adds 12.288 MHz suport to codec digital clk, this clock.
Some external PA requires a 12.288 MHz to work.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

This patch fixes missing mnd_width for codec_digital clk, this is now set to
8 inline with datasheet.

Fixes: 3966fab8 ("clk: qcom: Add MSM8916 Global Clock Controller support")
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

lpaif i2s clk rates in the freq table are not accurate enough
for I2S mclk. Fix the inaccurate ones and add few more clock
rates that are used in LPASS audio driver.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

Clkdiv module provides a clock output on the PMIC with CXO as
the source. This clock can be routed through PMIC GPIOs. Add
a device driver to configure this clkdiv module.
Signed-off-by: Tirupathi Reddy <tirupath@codeaurora.org>
[sboyd: Simplified code and moved to devm clk provider APIs]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

This patch adds device tree bindings for Qualcomm SPMI PMIC
clock divider module.
Signed-off-by: Tirupathi Reddy <tirupath@codeaurora.org>
[sboyd: Moved file to match compatible of binding]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

* clk-fixes:
  clk: fix a panic error caused by accessing NULL pointer
  clk: Manage proper runtime PM state in clk_change_rate()

In some cases the clock parent would be set NULL when doing re-parent,
it will cause a NULL pointer accessing if clk_set trace event is
enabled.

This patch sets the parent as "none" if the input parameter is NULL.

Fixes: dfc202ea (clk: Add tracepoints for hardware operations)
Signed-off-by: Cai Li <cai.li@spreadtrum.com>
Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

clk_change_rate() propagates rate change down to all its children. Such
operation requires managing proper runtime PM state of each child, what
was missing. Add needed calls to clk_pm_runtime*() to ensure that
set_rate() clock callback is called on runtime active clock.

This fixes following issue found on Exynos5433 TM2 board with devfreq
enabled:

Synchronous External Abort: synchronous external abort (0x96000210) at 0xffffff80093f5600
Internal error: : 96000210 [#1] PREEMPT SMP
Modules linked in:
CPU: 0 PID: 5 Comm: kworker/u16:0 Not tainted 4.15.0-rc1-next-20171129+ #4
Hardware name: Samsung TM2 board (DT)
Workqueue: devfreq_wq devfreq_monitor
task: ffffffc0ca96b600 task.stack: ffffff80093a8000
pstate: a0000085 (NzCv daIf -PAN -UAO)
pc : clk_divider_set_rate+0x54/0x118
lr : clk_divider_set_rate+0x44/0x118
...
Process kworker/u16:0 (pid: 5, stack limit = 0xffffff80093a8000)
Call trace:
 clk_divider_set_rate+0x54/0x118
 clk_change_rate+0xfc/0x4e0
 clk_change_rate+0x1f0/0x4e0
 clk_change_rate+0x1f0/0x4e0
 clk_change_rate+0x1f0/0x4e0
 clk_core_set_rate_nolock+0x138/0x148
 clk_set_rate+0x28/0x50
 exynos_bus_passive_target+0x6c/0x11c
 update_devfreq_passive+0x58/0xb4
 devfreq_passive_notifier_call+0x50/0x5c
 notifier_call_chain+0x4c/0x88
 __srcu_notifier_call_chain+0x54/0x80
 srcu_notifier_call_chain+0x14/0x1c
 update_devfreq+0x100/0x1b4
 devfreq_monitor+0x2c/0x88
 process_one_work+0x148/0x3d8
 worker_thread+0x13c/0x3f8
 kthread+0x100/0x12c
 ret_from_fork+0x10/0x18
Reported-by: Chanwoo Choi <cw00.choi@samsung.com>
Fixes: 9a34b453 ("clk: Add support for runtime PM")
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

Re-route all opt-clocks to use the new clkctrl clocks also, instead of
depending on the old dt clocks. Also, add aliases for certain clkctrl
clocks that hwmod core depends upon. The alias list can be stripped
down once hwmod database no longer needs these.
Signed-off-by: Tero Kristo <t-kristo@ti.com>

Add data for dm816 clkctrl clocks, and register it within the clkctrl
driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>

Contains offsets for all dm816 clkctrl main and optional clocks.
Signed-off-by: Tero Kristo <t-kristo@ti.com>

Add data for dm814 clkctrl clocks, and register it within the clkctrl
driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>

Contains offsets for all dm814 clkctrl main and optional clocks.
Signed-off-by: Tero Kristo <t-kristo@ti.com>

Add data for am43xx clkctrl clocks, and register it within the clkctrl
driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>

Contains offsets for all am43xx clkctrl main and optional clocks.
Signed-off-by: Tero Kristo <t-kristo@ti.com>

Add data for am33xx clkctrl clocks, and register it within the clkctrl
driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>

Contains offsets for all am33xx clkctrl main and optional clocks.
Signed-off-by: Tero Kristo <t-kristo@ti.com>

Add data for dra7 clkctrl clocks, and register it within the clkctrl
driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>

Contains offsets for all dra7 clkctrl main and optional clocks.
Signed-off-by: Tero Kristo <t-kristo@ti.com>

Add data for omap5 clkctrl clocks, and register it within the clkctrl
driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>

Contains offsets for all omap5 clkctrl main and optional clocks.
Signed-off-by: Tero Kristo <t-kristo@ti.com>

Most of the clock aliases are no longer needed, only leave the ones
required by OMAP timer code in place.
Signed-off-by: Tero Kristo <t-kristo@ti.com>

Most of the clock aliases are no longer needed, only leave the ones
required by OMAP timer code in place.
Signed-off-by: Tero Kristo <t-kristo@ti.com>

Most of the clock aliases are no longer needed, only leave the ones
required by OMAP timer code in place.
Signed-off-by: Tero Kristo <t-kristo@ti.com>

Most of the clock aliases are no longer needed, only leave the ones
required by OMAP timer code in place.
Signed-off-by: Tero Kristo <t-kristo@ti.com>