1. 05 Aug, 2003 1 commit
    • Kochi Takayoshi's avatar
      [PATCH] ia64: Interrupt polarity fix · 9072b37e
      Kochi Takayoshi authored
      It seems that acpi_register_intr (in arch/ia64/kernel/acpi.c)
      takes an interrupt polarity/trigger in opposite way.
      Attached patch fixes this.  Please apply.
      
      drivers/acpi/resource/rsirq.c decodes ACPI extended irq
      resource and stores in edge_level and active_high_low members
      of a structure (BTW, I think the names of these members
      are source of confusion ;).
      
      And this logic in acpi.c inverts both polarity and trigger.
      
      vector = iosapic_register_intr(gsi,
              polarity ? IOSAPIC_POL_HIGH : IOSAPIC_POL_LOW,
              mode ? IOSAPIC_EDGE : IOSAPIC_LEVEL);
      
             ACPI -> rsirq.c -> serial.c -> acpi.c            -> iosapic.c
      High      0         0           0      IOSAPIC_POL_LOW
      Low       1         1           1      IOSAPIC_POL_HIGH
      Edge      1         0           0      IOSAPIC_LEVEL
      Level     0         1           1      IOSAPIC_EDGE
      
      As ACPI_ACTIVE_{HIGH,LOW} and ACPI_{LEVEL,EDGE}_SENSITIVE are
      defined in acpi subsystem, it should be safer to use these symbols.
      9072b37e
  2. 04 Aug, 2003 4 commits
    • David Mosberger's avatar
      xtalk.h, sn_ksyms.c, sn2_smp.c, cache.c, shuberror.c, shub.c, iomv.c, hcl.c: · 7e3c70c0
      David Mosberger authored
        ia64: sn2 module (& other misc.) fixes
      7e3c70c0
    • David Mosberger's avatar
      ia64: Define fsid_t for kernel purposes. · d3b41f55
      David Mosberger authored
      d3b41f55
    • David Mosberger's avatar
      Many files: · 3801c3a6
      David Mosberger authored
        ia64: sn2 update
      .del-sv.h~583ade34a48fc2a0:
        Delete: include/asm-ia64/sn/sv.h
      .del-sv.c~37c4d6a1e76bdd1d:
        Delete: arch/ia64/sn/kernel/sv.c
      3801c3a6
    • Alex Williamson's avatar
      [PATCH] ia64: New CMC/CPE polling · 765a8447
      Alex Williamson authored
      Here's a redesign of the CMC and CPE polling for both 2.6.0-test2
      and 2.4.21.  This is roughly the same design I requested comment on
      a while back (BTW, nobody commented...).  Basically, rather than
      flooding all the cpus in parallel, I used some low priority interrupts
      to cascade through the cpus.  This should be much more scalable.  I
      also added a new feature of enabling interrupts for the CMC and CPE
      handlers.  The SAL spec claims these functions are SMP safe and
      re-entrant and even recommends that the corrected error handlers
      should run with interrupts enabled.  It works on HP boxes, others
      might want to double check that their firmware adheres to the spec.
      The combination of these things should keep polling from impacting
      system response time.
      765a8447
  3. 29 Jul, 2003 1 commit
  4. 28 Jul, 2003 2 commits
  5. 27 Jul, 2003 3 commits
  6. 26 Jul, 2003 29 commits