- 01 Jun, 2022 6 commits
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hengzhou authored
[WHY] Very low rate to cause memory access issue while resetting DMCUB after the halt command was sent to it. The process of stopping fw of DMCUB may be timeout, that means it is not in idle state, such as the window frames may still be kept in cache, so reset by force will cause MMHUB hang. [HOW] After the halt command was sent, keep checking the DMCUB state until it is idle. Reviewed-by:
Eric Yang <Eric.Yang2@amd.com> Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Jasdeep Dhillon <jdhillon@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
hengzhou <Hengyong.Zhou@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Nicholas Kazlauskas authored
[Why] When enabling an HPO stream for the first time after having previously enabled a DIO stream there may be lingering DIO FIFO errors even though the DIO is no longer enabled. These can cause display clock change to hang if we don't apply the OTG disable workaround since the ramping logic is tied to OTG on. [How] The workaround wasn't being applied in the sequence of: 1 DIO stream 0 streams 1 HPO stream because current_state has no stream or planes in its context - and it's only swapped after optimize has finished. We should be using the incoming context instead to determine whether this logic is needed or not. Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
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Leung, Martin authored
why and how: Revert this change. It was causing a black screen with certain blocks Reviewed-by:
George Shen <George.Shen@amd.com> Acked-by:
Leung, Martin <Martin.Leung@amd.com> Signed-off-by:
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Sherry Wang authored
[Why] Dmub read AUX_DPHY_RX_CONTROL0 from Golden Setting Table, but driver will set it to default value 0x103d1110, which causes issue in some case [How] Remove the driver code, use the value set by dmub in dp_aux_init Reviewed-by:
Sherry Wang <YAO.WANG1@amd.com> Signed-off-by:
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Dave Airlie authored
Merge tag 'amd-drm-next-5.19-2022-05-26-2' of https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-5.19-2022-05-26-2: amdgpu: - Update fdinfo to the common drm format UAPI: - Add VM_NOALLOC GPUVM attribute to prevent buffers for going into the MALL Add AMDGPU_GEM_CREATE_DISCARDABLE flag to create buffers that can be discarded on eviction Mesa code which uses these: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16466Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220526202546.66860-1-alexander.deucher@amd.com
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Dave Airlie authored
Merge tag 'amd-drm-next-5.19-2022-05-26' of https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-5.19-2022-05-26: amdgpu: - Link training fixes - DPIA fixes - Misc code cleanups - Aux fixes - Hotplug fixes - More FP clean up - Misc GFX9/10 fixes - Fix a possible memory leak in SMU shutdown - SMU 13 updates - RAS fixes - TMZ fixes - GC 11 updates - SMU 11 metrics fixes - Fix coverage blend mode for overlay plane - Note DDR vs LPDDR memory - Fuzz fix for CS IOCTL - Add new PCI DID amdkfd: - Clean up hive setup - Misc fixes radeon: - Fix a possible NULL pointer dereference Signed-off-by:
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- 26 May, 2022 34 commits
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Christian König authored
This is enough to get gputop working :) v2: rebase and some addition cleanup Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by: Shashank Sharma <shashank.sharma@amd.com> (v1) Signed-off-by:
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Christian König authored
Convert fdinfo format to one documented in drm-usage-stats.rst. It turned out that the existing implementation was actually completely nonsense. The calculated percentages indeed represented the usage of the engine, but with varying time slices. So 10% usage for application A could mean something completely different than 10% usage for application B. Completely nuke that and just use the now standardized nanosecond interface. v2: drop the documentation change for now, nuke percentage calculation v3: only account for each hw_ip, move the time_spend to the ctx mgr. v4: move general ctx changes into separate patch, rework the fdinfo to ctx_mgr interface so that all usages are calculated at once, drop some unecessary and dangerous refcount dance. v5: add one more comment how we calculate the time spend Signed-off-by:Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by:
Shashank Sharma <shashank.sharma@amd.com> Cc: Daniel Vetter <daniel@ffwll.ch> Signed-off-by:
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Christian König authored
Increase the minor version number to indicate that the new flags are available. Signed-off-by:
Marek Olšák <marek.olsak@amd.com> Signed-off-by:
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Christian König authored
Add the AMDGPU_VM_NOALLOC flag to let userspace control MALL allocation. v2: also add the flag to the allowed flags. Signed-off-by:
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Christian König authored
Add a AMDGPU_GEM_CREATE_DISCARDABLE flag to note that the content of a BO doesn't needs to be preserved during eviction. KFD was already using a similar functionality for SVM BOs so replace the internal flag with the new UAPI. Signed-off-by:
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Alex Deucher authored
Add a beige goby PCI ID. Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Lijo Lazar authored
When powerplay is not enabled, return AUTO as default level. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Acked-by:
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Julia Lawall authored
Spelling mistake (triple letters) in comment. Detected with the help of Coccinelle. Signed-off-by:
Julia Lawall <Julia.Lawall@inria.fr> Signed-off-by:
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Julia Lawall authored
Spelling mistakes (triple letters) in comments. Detected with the help of Coccinelle. Signed-off-by:
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Dave Airlie authored
Submitting a cs with 0 chunks, causes an oops later, found trying to execute the wrong userspace driver. MESA_LOADER_DRIVER_OVERRIDE=v3d glxinfo [172536.665184] BUG: kernel NULL pointer dereference, address: 00000000000001d8 [172536.665188] #PF: supervisor read access in kernel mode [172536.665189] #PF: error_code(0x0000) - not-present page [172536.665191] PGD 6712a0067 P4D 6712a0067 PUD 5af9ff067 PMD 0 [172536.665195] Oops: 0000 [#1] SMP NOPTI [172536.665197] CPU: 7 PID: 2769838 Comm: glxinfo Tainted: P O 5.10.81 #1-NixOS [172536.665199] Hardware name: To be filled by O.E.M. To be filled by O.E.M./CROSSHAIR V FORMULA-Z, BIOS 2201 03/23/2015 [172536.665272] RIP: 0010:amdgpu_cs_ioctl+0x96/0x1ce0 [amdgpu] [172536.665274] Code: 75 18 00 00 4c 8b b2 88 00 00 00 8b 46 08 48 89 54 24 68 49 89 f7 4c 89 5c 24 60 31 d2 4c 89 74 24 30 85 c0 0f 85 c0 01 00 00 <48> 83 ba d8 01 00 00 00 48 8b b4 24 90 00 00 00 74 16 48 8b 46 10 [172536.665276] RSP: 0018:ffffb47c0e81bbe0 EFLAGS: 00010246 [172536.665277] RAX: 0000000000000000 RBX: 0000000000000000 RCX: 0000000000000000 [172536.665278] RDX: 0000000000000000 RSI: ffffb47c0e81be28 RDI: ffffb47c0e81bd68 [172536.665279] RBP: ffff936524080010 R08: 0000000000000000 R09: ffffb47c0e81be38 [172536.665281] R10: ffff936524080010 R11: ffff936524080000 R12: ffffb47c0e81bc40 [172536.665282] R13: ffffb47c0e81be28 R14: ffff9367bc410000 R15: ffffb47c0e81be28 [172536.665283] FS: 00007fe35e05d740(0000) GS:ffff936c1edc0000(0000) knlGS:0000000000000000 [172536.665284] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [172536.665286] CR2: 00000000000001d8 CR3: 0000000532e46000 CR4: 00000000000406e0 [172536.665287] Call Trace: [172536.665322] ? amdgpu_cs_find_mapping+0x110/0x110 [amdgpu] [172536.665332] drm_ioctl_kernel+0xaa/0xf0 [drm] [172536.665338] drm_ioctl+0x201/0x3b0 [drm] [172536.665369] ? amdgpu_cs_find_mapping+0x110/0x110 [amdgpu] [172536.665372] ? selinux_file_ioctl+0x135/0x230 [172536.665399] amdgpu_drm_ioctl+0x49/0x80 [amdgpu] [172536.665403] __x64_sys_ioctl+0x83/0xb0 [172536.665406] do_syscall_64+0x33/0x40 [172536.665409] entry_SYSCALL_64_after_hwframe+0x44/0xa9 Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2018Signed-off-by:
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Alex Deucher authored
Some applications want to know whether the memory is LP or not. Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Candice Li authored
Check shared buf instead of init flag for xgmi ta shared buf init during xgmi ta initialization. Signed-off-by:
Candice Li <candice.li@amd.com> Reviewed-by:
John Clements <john.clements@amd.com> Signed-off-by:
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Prike Liang authored
On the psp13 series use ta_firmware_header_v2_0 and the asd firmware was buildin ta, so needn't request asd firmware separately. Signed-off-by:
Prike Liang <Prike.Liang@amd.com> Reviewed-by:
Yifan Zhang <yifan1.zhang@amd.com> Acked-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Alex Deucher authored
Validate the VCN and SDMA instances against the driver structure sizes to make sure we don't get into a situation where the firmware reports more instances than the driver supports. Reviewed-by:
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Sung Joon Kim authored
According to the KMS man page, there is a "Coverage" alpha blend mode that assumes the pixel color values have NOT been pre-multiplied and will be done when the actual blending to the background color values happens. Previously, this mode hasn't been enabled in our driver and it was assumed that all normal overlay planes are pre-multiplied by default. When a 3rd party app is used to input a image in a specific format, e.g. PNG, as a source of a overlay plane to blend with the background primary plane, the pixel color values are not pre-multiplied. So by adding "Coverage" blend mode, our driver will support those cases. Issue fixed: Overlay plane alpha channel blending is incorrect Issue tracker: https://gitlab.freedesktop.org/drm/amd/-/issues/1769 Reference: https://dri.freedesktop.org/docs/drm/gpu/drm-kms.html#plane-composition-properties Adding Coverage support also enables IGT kms_plane_alpha_blend Coverage subtests: 1. coverage-7efc 2. coverage-vs-premult-vs-constant Changes 1. Add DRM_MODE_BLEND_COVERAGE blend mode capability 2. Add "pre_multiplied_alpha" flag for Coverage case 3. Read the correct flag and set the DCN MPCC pre_multiplied register bit (only on overlay plane) Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1769Signed-off-by:
Sung Joon Kim <Sungjoon.Kim@amd.com> Reviewed-by:
Melissa Wen <mwen@igalia.com> Signed-off-by:
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Dan Carpenter authored
The > ARRAY_SIZE() should be >= ARRAY_SIZE() to prevent an out of bounds access. Fixes: e27c41d5 ("drm/amd/display: Support for DMUB HPD interrupt handling") Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
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Evan Quan authored
Suppress two compile warnings about "no previous prototype". Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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Evan Quan authored
Correct the metrics version used for SMU 11.0.11/12/13. Fixes misreported GPU metrics (e.g., fan speed, etc.) depending on which version of SMU firmware is loaded. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1925Signed-off-by:
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Jay Cornwall authored
Based on gfx10 with following changes: - GPR_ALLOC.VGPR_SIZE field moved (and size corrected in gfx10) - s_sendmsg_rtn_b64 replaces some s_sendmsg/s_getreg - Buffer instructions no longer have direct-to-LDS modifier Signed-off-by:
Jay Cornwall <jay.cornwall@amd.com> Reviewed-by:
Laurent Morichetti <laurent.morichetti@amd.com> Signed-off-by:
Eric Huang <jinhuieric.huang@amd.com> Acked-by:
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Eric Huang authored
Most of changes are for debugger feature, and it is to simplify trap handler support for new asics in the future. Signed-off-by:
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Alan Liu authored
Define HDMI_ACP_SEND register shift/mask. Signed-off-by:
Alan Liu <HaoPing.Liu@amd.com> Reviewed-by:
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Lijo Lazar authored
On aldebaran, when thermal throttling happens due to excessive GPU temperature, the reason for throttling event is missed in warning message. This patch fixes it. Signed-off-by:
Yang Wang <kevinyang.wang@amd.com> Signed-off-by:
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Sunil Khatri authored
Add support of IP GC 10.3.7 in amdgpu_gmc_tmz_set. Signed-off-by:
Sunil Khatri <sunil.khatri@amd.com> Reviewed-by:
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Sunil Khatri authored
Use IP version rather then code name of IPs for tmz set. Signed-off-by:
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Sunil Khatri authored
To enable TMZ feature based on IP version needs adev->ip_version populated but its empty. Move amdgpu_gmc_tmz_set to a place where ip_version is populated. Signed-off-by:
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Stanley.Yang authored
support umc/gfx/sdma ras on guest side Changed from V1: move sriov judgment in amdgpu_ras_interrupt_fatal_error_handler Signed-off-by:Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Dan Carpenter authored
There is no need to check if "clock_ranges' is non-NULL. It is checked already on the line before. Signed-off-by:
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Evan Quan authored
With the latest vbios, the memory temp reading is working. Signed-off-by:
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Evan Quan authored
Enable OOB Monitor and SOC CG which are ready since 78.38.0. Signed-off-by:
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Evan Quan authored
To better match with the pptable_id settings from VBIOS. Signed-off-by:
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Evan Quan authored
To align with 78.37.0 and later PMFWs. Signed-off-by:
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Evan Quan authored
Since PMFW will handle this properly. Driver involvement is unnecessary. Signed-off-by:
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Evan Quan authored
Enable MP0CLK DPM and FW Dstate since they are already supported by latest 78.36.0 PMFW. Signed-off-by:
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Gong Yuanjun authored
gpu_metrics_table is allocated in yellow_carp_init_smc_tables() but not freed in yellow_carp_fini_smc_tables(). Signed-off-by:
Gong Yuanjun <ruc_gongyuanjun@163.com> Signed-off-by:
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