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  1. 06 Sep, 2012 7 commits
    • Prashant Gaikwad's avatar
      ARM: tegra: Port tegra to generic clock framework · 92fe58f0
      Prashant Gaikwad authored 
      This patch converts tegra clock code to generic clock framework in following way:
 - Implement clk_ops as required by generic clk framework. (tegraXX_clocks.c)
 - Use platform specific struct clk_tegra in clk_ops implementation instead of struct clk.
 - Initialize all clock data statically. (tegraXX_clocks_data.c)

Legacy framework did not have recalc_rate and is_enabled functions. Implemented these functions.
Removed init function. It's functionality is splitted into recalc_rate and is_enabled.

Static initialization is used since slab is not up in .init_early and clock
is needed to be initialized before clockevent/clocksource initialization.
Macros redefined for clk_tegra.

Also, single struct clk_tegra is used for all type of clocks (PLL, peripheral etc.). This
is to move quickly to generic common clock framework so that other dependent features will
not be blocked (such as DT binding).

Enabling COMMON_CLOCK config moved to ARCH_TEGRA since it is enabled for both Tegra20
and Tegra30.
Signed-off-by: default avatarPrashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
      92fe58f0
    • Prashant Gaikwad's avatar
      ARM: tegra: Add clk_tegra structure and helper functions · 96a1bd1e
      Prashant Gaikwad authored 
      Add Tegra platform specific clock structure clk_tegra and
some helper functions for generic clock framework.

struct clk_tegra is the single strcture used for all types of
clocks. reset and cfg_ex ops moved to clk_tegra from clk_ops.
Signed-off-by: default avatarPrashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
      96a1bd1e
    • Prashant Gaikwad's avatar
      ARM: tegra: Rename tegra20 clock file · 23fc5b24
      Prashant Gaikwad authored 
      Make the name consistent with other files.
s/tegra2/tegra20
Signed-off-by: default avatarPrashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
      23fc5b24
    • Prashant Gaikwad's avatar
      ARM: tegra20: Separate out clk ops and clk data · 86edb87a
      Prashant Gaikwad authored 
      Move clock initialization data to separate file. This is
required for migrating to generic clock framework if static
initialization is used.
Signed-off-by: default avatarPrashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
      86edb87a
    • Prashant Gaikwad's avatar
      ARM: tegra30: Separate out clk ops and clk data · 88e790a4
      Prashant Gaikwad authored 
      Move clock initialization data to separate file. This is
required for migrating to generic clock framework if static
initialization is used.
Signed-off-by: default avatarPrashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
      88e790a4
    • Stephen Warren's avatar
      ARM: tegra: fix U16 divider range check · eb70e1bd
      Stephen Warren authored 
      A U16 divider can divide a clock by 1..64K. However, the range-check
in clk_div16_get_divider() limited the range to 1..256. Fix this. NVIDIA's
downstream kernels already have the fixed range-check.

In practice this is a problem on Whistler's I2C bus, which uses a bus
clock rate of 100KHz (rather than the more common 400KHz on Tegra boards),
which requires a HW module clock of 8*100KHz. The parent clock is 216MHz,
leading to a desired divider of 270. Prior to conversion to the common
clock framework, this range error was somehow ignored/irrelevant and
caused no problems. However, the common clock framework evidently has
more rigorous error-checking, so this failure causes the I2C bus to fail
to operate correctly.
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
      eb70e1bd
    • Stephen Warren's avatar
      ARM: tegra: turn on UART A clock at boot · 37c241ed
      Stephen Warren authored 
      Some boards use UART D for the main serial console, and some use UART A.
UART D's clock is listed in board-dt-tegra20.c's clock table, whereas
UART A's clock is not. This causes the clock code to think UART A's
clock is unsed. The common clock framework turns off unused clocks at
boot time. This makes the kernel appear to hang. Add UART A's clock into
the clock table to prevent this. Eventually, this requirement should be
handled by the UART driver, and/or properties in a board-specific device
tree file.
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
      37c241ed
  3. 01 Sep, 2012 5 commits
  5. 30 Aug, 2012 5 commits
  7. 29 Aug, 2012 18 commits
  9. 28 Aug, 2012 5 commits
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